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architecture Behavioral of baud_generator is
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architecture Behavioral of baud_generator is
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signal genTick : std_logic;
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signal genTick : std_logic;
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signal genTickOverSample : std_logic;
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signal genTickOverSample : std_logic;
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begin
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begin
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process (rst, clk)
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process (rst, clk, cycle_wait)
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variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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wait_clk_cycles := (others => '0');
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wait_clk_cycles := (others => '0');
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baud <= genTick;
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baud <= genTick;
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baud_oversample <= genTickOverSample;
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baud_oversample <= genTickOverSample;
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-- Process to generate the overclocked (8x) sample
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-- Process to generate the overclocked (8x) sample
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process (rst, clk)
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process (rst, clk, cycle_wait)
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variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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