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--! Baud generator
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--! @file
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--! http://www.fpga4fun.com/SerialInterface.html
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--! @brief Baud generator http://www.fpga4fun.com/SerialInterface.html
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity baud_generator is
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entity baud_generator is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Reset Input
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Clock input
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
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baud_oversample : out std_logic;
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baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
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baud : out STD_LOGIC);
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baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
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end baud_generator;
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end baud_generator;
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--! @brief Baud generator http://www.fpga4fun.com/SerialInterface.html
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--! @details Implement block that will generate the desired baud (115200, 9600, etc...) from main clock (50Mhz)
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architecture Behavioral of baud_generator is
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architecture Behavioral of baud_generator is
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signal genTick : std_logic;
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signal genTick : std_logic;
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signal genTickOverSample : std_logic;
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signal genTickOverSample : std_logic;
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begin
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begin
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process (rst, clk, cycle_wait)
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process (rst, clk, cycle_wait)
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