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| Rev 6 |
Rev 8 |
| Line 25... |
Line 25... |
if rst = '1' then
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if rst = '1' then
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wait_clk_cycles := (others => '0');
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wait_clk_cycles := (others => '0');
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half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
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half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
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genTick <= '0';
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genTick <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if wait_clk_cycles = cycle_wait then
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-- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
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-- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
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if wait_clk_cycles = (cycle_wait - conv_std_logic_vector(1, (nBitsLarge-1))) then
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genTick <= '1';
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genTick <= '1';
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wait_clk_cycles := (others => '0');
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wait_clk_cycles := (others => '0');
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else
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else
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wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
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wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
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-- If we're at half of the cycle
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-- If we're at half of the cycle
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