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--! http://en.wikipedia.org/wiki/Division_%28digital%29
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--! http://en.wikipedia.org/wiki/Division_%28digital%29
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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entity divisor is
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entity divisor is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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quotient : out STD_LOGIC_VECTOR (31 downto 0);
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR (31 downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR (31 downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR (31 downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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done : out STD_LOGIC);
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done : out STD_LOGIC);
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end divisor;
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end divisor;
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architecture Behavioral of divisor is
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architecture Behavioral of divisor is
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