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Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testDivisor_beh.prj testDivisor
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Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
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ISim O.87xd (signature 0xc3576ebc)
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ISim O.87xd (signature 0x8ddf5b5d)
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Number of CPUs detected in this system: 8
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 16
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Determining compilation order of HDL files
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Determining compilation order of HDL files
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Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/testDivisor.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
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Starting static elaboration
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Starting static elaboration
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Completed static elaboration
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Completed static elaboration
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Fuse Memory Usage: 36024 KB
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Fuse CPU Usage: 1120 ms
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Compiling package standard
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Compiling package standard
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Compiling package std_logic_1164
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Compiling package std_logic_1164
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Compiling package std_logic_arith
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Compiling package pkgdefinitions
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Compiling package pkgdefinitions
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Compiling architecture behavioral of entity divisor [divisor_default]
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Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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Compiling architecture behavior of entity testdivisor
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Compiling architecture behavior of entity testserial_receiver
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Time Resolution for simulation is 1ps.
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 6 VHDL Units
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Compiled 7 VHDL Units
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
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Built simulation executable E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe
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Fuse Memory Usage: 79448 KB
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Fuse Memory Usage: 33532 KB
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Fuse CPU Usage: 1150 ms
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Fuse CPU Usage: 264 ms
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GCC CPU Usage: 310 ms
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GCC CPU Usage: 310 ms
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GCC CPU Usage: 310 ms
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