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Line 8... |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work
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Starting static elaboration
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Starting static elaboration
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Completed static elaboration
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Completed static elaboration
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Fuse Memory Usage: 36628 KB
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Fuse Memory Usage: 36628 KB
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Fuse CPU Usage: 1070 ms
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Fuse CPU Usage: 1090 ms
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Compiling package standard
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Compiling package standard
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Compiling package std_logic_1164
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Compiling package std_logic_1164
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Compiling package std_logic_arith
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Compiling package std_logic_arith
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Compiling package std_logic_unsigned
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Compiling package std_logic_unsigned
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Compiling package pkgdefinitions
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Compiling package pkgdefinitions
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Compiling architecture behavioral of entity divisor [divisor_default]
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Compiling architecture behavioral of entity divisor [divisor_default]
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Compiling architecture behavioral of entity uart_control [uart_control_default]
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Compiling architecture behavioral of entity uart_control [uart_control_default]
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Compiling architecture behavior of entity testuart_control
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Compiling architecture behavior of entity testuart_control
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Time Resolution for simulation is 1ps.
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 10 VHDL Units
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Compiled 10 VHDL Units
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
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Fuse Memory Usage: 85688 KB
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Fuse Memory Usage: 85688 KB
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Fuse CPU Usage: 1160 ms
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Fuse CPU Usage: 1180 ms
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GCC CPU Usage: 400 ms
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GCC CPU Usage: 400 ms
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