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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [fuse.log] - Diff between revs 20 and 21

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Rev 20 Rev 21
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Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj work.testUart_control
ISim O.87xd (signature 0xc3576ebc)
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 8
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
 
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
 
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
 
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression
 
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
 
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
 
Starting static elaboration
Starting static elaboration
Completed static elaboration
Completed static elaboration
 
Fuse Memory Usage: 36628 KB
 
Fuse CPU Usage: 1100 ms
Compiling package standard
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling package numeric_std
Compiling architecture behavior of entity testuart_control
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
 
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
 
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
 
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
 
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
 
Compiling architecture behavior of entity testuart_wishbone_slave
 
Time Resolution for simulation is 1ps.
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Waiting for 1 sub-compilation(s) to finish...
Compiled 21 VHDL Units
Compiled 10 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
Fuse Memory Usage: 37372 KB
Fuse Memory Usage: 85692 KB
Fuse CPU Usage: 420 ms
Fuse CPU Usage: 1180 ms
 
GCC CPU Usage: 400 ms

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