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Line 1... |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
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Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -relaunch -intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave"
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ISim O.87xd (signature 0x8ddf5b5d)
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ISim O.87xd (signature 0x8ddf5b5d)
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Number of CPUs detected in this system: 4
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Determining compilation order of HDL files
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Determining compilation order of HDL files
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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| Line 14... |
Line 14... |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
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Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
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Starting static elaboration
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Starting static elaboration
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Completed static elaboration
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Completed static elaboration
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Fuse Memory Usage: 37476 KB
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Fuse Memory Usage: 37476 KB
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Fuse CPU Usage: 1100 ms
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Fuse CPU Usage: 1090 ms
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Compiling package standard
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Compiling package standard
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Compiling package std_logic_1164
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Compiling package std_logic_1164
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Compiling package std_logic_arith
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Compiling package std_logic_arith
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Compiling package std_logic_unsigned
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Compiling package std_logic_unsigned
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Compiling package pkgdefinitions
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Compiling package pkgdefinitions
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Line 30... |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
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Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
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Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
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Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
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Compiling architecture behavior of entity testuart_wishbone_slave
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Compiling architecture behavior of entity testuart_wishbone_slave
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Time Resolution for simulation is 1ps.
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 21 VHDL Units
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Compiled 21 VHDL Units
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
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Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
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Fuse Memory Usage: 91188 KB
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Fuse Memory Usage: 89272 KB
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Fuse CPU Usage: 1280 ms
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Fuse CPU Usage: 1260 ms
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GCC CPU Usage: 710 ms
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GCC CPU Usage: 260 ms
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GCC CPU Usage: 260 ms
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GCC CPU Usage: 260 ms
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