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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [fuse.log] - Diff between revs 3 and 4

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Rev 3 Rev 4
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Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver"
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
ISim O.87xd (signature 0xc3576ebc)
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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Compiling architecture behavior of entity testserial_receiver
Compiling architecture behavior of entity testserial_receiver
Time Resolution for simulation is 1ps.
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Compiled 6 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 29524 KB
Fuse Memory Usage: 29488 KB
Fuse CPU Usage: 264 ms
Fuse CPU Usage: 249 ms
Fuse CPU Usage: 249 ms
Fuse CPU Usage: 249 ms

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