URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Show entire file |
Details |
Blame |
View Log
Rev 39 |
Rev 40 |
Line 109... |
Line 109... |
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
|
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
|
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral
|
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral
|
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral
|
/testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral
|
|
|
|
|
testSerial_transmitter - behavior (E:/uart_block/hdl/iseProject/testSerial_transmitter.vhd)
|
testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)
|
|
|
0
|
0
|
0
|
0
|
000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003
|
000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003
|
true
|
true
|
testSerial_transmitter - behavior (E:/uart_block/hdl/iseProject/testSerial_transmitter.vhd)
|
testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)
|
|
|
|
|
|
|
1
|
1
|
Design Utilities
|
Design Utilities
|
Line 178... |
Line 178... |
|
|
1
|
1
|
User Constraints
|
User Constraints
|
|
|
|
|
|
|
|
|
0
|
0
|
0
|
0
|
000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000
|
000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000
|
false
|
false
|
|
|
|
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.