| Line 1... |
Line 1... |
ISim log file
|
ISim log file
|
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
|
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
|
ISim O.87xd (signature 0x8ddf5b5d)
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
Time resolution is 1 ps
|
Time resolution is 1 ps
|
| Line 15... |
Line 15... |
** Failure:NONE. End of simulation.
|
** Failure:NONE. End of simulation.
|
User(VHDL) Code Called Simulation Stop
|
User(VHDL) Code Called Simulation Stop
|
In process testUart_wishbone_slave.vhd:stim_proc
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
INFO: Simulator is stopped.
|
INFO: Simulator is stopped.
|
ISim O.87xd (signature 0x8ddf5b5d)
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 30
|
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
|
# run all
|
# run all
|
Stopped at time : 24706500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
|
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
|
# run all
|
# run all
|
Stopped at time : 25249500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
|
|
|
** Failure:NONE. End of simulation.
|
|
User(VHDL) Code Called Simulation Stop
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
|
INFO: Simulator is stopped.
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
|
# run all
|
# run all
|
Stopped at time : 25792500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
|
|
ISim O.87xd (signature 0x8ddf5b5d)
|
** Failure:NONE. End of simulation.
|
|
User(VHDL) Code Called Simulation Stop
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
|
INFO: Simulator is stopped.
|
|
# show driver /testuart_wishbone_slave/dat_o0
|
|
Driver for /testuart_wishbone_slave/dat_o0[0]
|
|
'1' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[10]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[11]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[12]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[13]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[14]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[15]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[16]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[17]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[18]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[19]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[1]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[20]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[21]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[22]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[23]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[24]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[25]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[26]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[27]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[28]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[29]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[2]
|
|
'1' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[30]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[31]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[3]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[4]
|
|
'1' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[5]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[6]
|
|
'1' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[7]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[8]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
Driver for /testuart_wishbone_slave/dat_o0[9]
|
|
'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
|
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
|
|
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
# run all
|
# run all
|
Stopped at time : 1821 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 46
|
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
# run all
|
# run all
|
Stopped at time : 8765 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 87
|
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
# run all
|
# run all
|
|
|
** Failure:NONE. End of simulation.
|
** Failure:NONE. End of simulation.
|
User(VHDL) Code Called Simulation Stop
|
User(VHDL) Code Called Simulation Stop
|
In process testUart_wishbone_slave.vhd:stim_proc
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
INFO: Simulator is stopped.
|
INFO: Simulator is stopped.
|
ISim O.87xd (signature 0x8ddf5b5d)
|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
|
# run all
|
|
|
** Failure:NONE. End of simulation.
|
** Failure:NONE. End of simulation.
|
User(VHDL) Code Called Simulation Stop
|
User(VHDL) Code Called Simulation Stop
|
In process testUart_wishbone_slave.vhd:stim_proc
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
INFO: Simulator is stopped.
|
INFO: Simulator is stopped.
|
ISim O.87xd (signature 0x8ddf5b5d)
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
ISim O.87xd (signature 0x8ddf5b5d)
|
# run all
|
|
|
|
** Failure:NONE. End of simulation.
|
|
User(VHDL) Code Called Simulation Stop
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
|
INFO: Simulator is stopped.
|
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
Stopped at time : 870 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
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Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
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# run all
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# run all
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** Failure:NONE. End of simulation.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
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This is a Lite version of ISim.
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# run 1000 ms
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 9627710 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" Line 60
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Stopped at time : 26193350 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
|
ISim O.87xd (signature 0x8ddf5b5d)
|
ISim O.87xd (signature 0xc3576ebc)
|
WARNING: A WEBPACK license was found.
|
WARNING: A WEBPACK license was found.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
This is a Lite version of ISim.
|
This is a Lite version of ISim.
|
# run 1000 ms
|
# run 1000 ms
|
Simulator is doing circuit initialization process.
|
Simulator is doing circuit initialization process.
|
Finished circuit initialization process.
|
Finished circuit initialization process.
|
Stopped at time : 87690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 125
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Stopped at time : 36542110 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
|
# run all
|
ISim O.87xd (signature 0xc3576ebc)
|
Stopped at time : 96330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 91
|
WARNING: A WEBPACK license was found.
|
# run all
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
Stopped at time : 105010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 96
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
# run all
|
This is a Lite version of ISim.
|
Stopped at time : 113690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 101
|
# run 1000 ms
|
# run all
|
Simulator is doing circuit initialization process.
|
Stopped at time : 122370 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 106
|
Finished circuit initialization process.
|
# run all
|
Stopped at time : 23647410 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 82
|
Stopped at time : 131050 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 111
|
ISim O.87xd (signature 0xc3576ebc)
|
# run all
|
WARNING: A WEBPACK license was found.
|
Stopped at time : 139730 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 116
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
# run all
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
Stopped at time : 148410 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 121
|
This is a Lite version of ISim.
|
# run all
|
# run 1000 ms
|
Stopped at time : 157090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 126
|
Simulator is doing circuit initialization process.
|
# run all
|
Finished circuit initialization process.
|
Stopped at time : 165770 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 132
|
Stopped at time : 16400510 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 89
|
# run all
|
ISim O.87xd (signature 0xc3576ebc)
|
Stopped at time : 9633330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 71
|
WARNING: A WEBPACK license was found.
|
# exit 0
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 ms
|
|
Simulator is doing circuit initialization process.
|
|
Finished circuit initialization process.
|
|
|
|
** Failure:NONE. End of simulation.
|
|
User(VHDL) Code Called Simulation Stop
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
|
|
|
INFO: Simulator is stopped.
|
