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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Diff between revs 19 and 20

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Rev 19 Rev 20
Line 15... Line 15... 
** Failure:NONE. End of simulation.
 
** Failure:NONE. End of simulation.
 
User(VHDL) Code Called Simulation Stop
 
User(VHDL) Code Called Simulation Stop
 
In process testUart_wishbone_slave.vhd:stim_proc
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
INFO: Simulator is stopped.
 
INFO: Simulator is stopped.
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
 
 
 
# run all
 
 
 
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
# show driver /testuart_wishbone_slave/dat_o0
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[0]
 
 
 
        '1'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[10]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[11]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[12]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[13]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[14]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[15]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[16]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[17]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[18]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[19]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[1]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[20]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[21]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[22]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[23]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[24]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[25]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[26]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[27]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[28]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[29]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[2]
 
 
 
        '1'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[30]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[31]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[3]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[4]
 
 
 
        '1'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[5]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[6]
 
 
 
        '1'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[7]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[8]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
Driver for /testuart_wishbone_slave/dat_o0[9]
 
 
 
        '0'     : /testuart_wishbone_slave/uut/uUartControl/:64
 
 
 
                  in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
 
 
 
 
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
 
 
 
# run all
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 26193350 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 36542110 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 23647410 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 82
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
Stopped at time : 16400510 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 89
 
 
 
ISim O.87xd (signature 0xc3576ebc)
 
 
 
WARNING: A WEBPACK license was found.
 
 
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
 
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
 
 
This is a Lite version of ISim.
 
 
 
# run 1000 ms
 
 
 
Simulator is doing circuit initialization process.
 
 
 
Finished circuit initialization process.
 
 
 
 
 
 
 
** Failure:NONE. End of simulation.
 
 
 
User(VHDL) Code Called Simulation Stop
 
 
 
In process testUart_wishbone_slave.vhd:stim_proc
 
 
 
 
 
 
 
INFO: Simulator is stopped.
 
 

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