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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Diff between revs 20 and 21

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Rev 20 Rev 21
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ISim log file
 
ISim log file
 
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
 
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.wdb
 
ISim O.87xd (signature 0xc3576ebc)
 
ISim O.87xd (signature 0x8ddf5b5d)
 
WARNING: A WEBPACK license was found.
 
WARNING: A WEBPACK license was found.
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
 
This is a Lite version of ISim.
 
This is a Lite version of ISim.
 
Time resolution is 1 ps
 
Time resolution is 1 ps
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Simulator is doing circuit initialization process.
 
Simulator is doing circuit initialization process.
 
Finished circuit initialization process.
 
Finished circuit initialization process.
 
 
 
 
 
** Failure:NONE. End of simulation.
 
** Failure:NONE. End of simulation.
 
User(VHDL) Code Called Simulation Stop
 
User(VHDL) Code Called Simulation Stop
 
In process testUart_wishbone_slave.vhd:stim_proc
 
In process testUart_control.vhd:stim_proc
 
 
 
 
 
INFO: Simulator is stopped.
 
INFO: Simulator is stopped.
 
 
 
# exit 0

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