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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Diff between revs 21 and 22

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Rev 21 Rev 22
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ISim log file
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.wdb
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
This is a Lite version of ISim.
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# onerror resume
# onerror resume
# wave add /
# wave add /
# run 1000 ms
# run 1000 ms
Simulator is doing circuit initialization process.
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Finished circuit initialization process.
 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
 
** Failure:NONE. End of simulation.
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
User(VHDL) Code Called Simulation Stop
In process testUart_control.vhd:stim_proc
In process testUart_wishbone_slave.vhd:stim_proc
 
 
INFO: Simulator is stopped.
INFO: Simulator is stopped.
# exit 0
# exit 0

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