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ISim log file
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ISim log file
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Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.wdb
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Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
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ISim O.87xd (signature 0x8ddf5b5d)
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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This is a Lite version of ISim.
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# onerror resume
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# onerror resume
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# wave add /
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# wave add /
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# run 1000 ms
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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User(VHDL) Code Called Simulation Stop
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In process testUart_control.vhd:stim_proc
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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INFO: Simulator is stopped.
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# exit 0
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# exit 0
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