Line 15... |
Line 15... |
** Failure:NONE. End of simulation.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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User(VHDL) Code Called Simulation Stop
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In process testSerial_receiver.vhd:stim_proc
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In process testSerial_receiver.vhd:stim_proc
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INFO: Simulator is stopped.
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 us
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testSerial_receiver.vhd:stim_proc
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INFO: Simulator is stopped.
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|
ISim O.87xd (signature 0xc3576ebc)
|
|
WARNING: A WEBPACK license was found.
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
|
This is a Lite version of ISim.
|
|
# run 1000 us
|
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testSerial_receiver.vhd:stim_proc
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INFO: Simulator is stopped.
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