| Line 1... |
Line 1... |
Release 13.4 - xst O.87xd (nt64)
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Release 13.4 - xst O.87xd (lin)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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Total CPU time to Xst completion: 0.05 secs
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--> Parameter xsthdpdir set to xst
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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Total CPU time to Xst completion: 0.05 secs
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--> Reading design: serial_receiver.prj
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-->
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Reading design: serial_receiver.prj
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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1) Synthesis Options Summary
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2) HDL Compilation
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2) HDL Compilation
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3) Design Hierarchy Analysis
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3) Design Hierarchy Analysis
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| Line 102... |
Line 105... |
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=========================================================================
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=========================================================================
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* HDL Compilation *
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* HDL Compilation *
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=========================================================================
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=========================================================================
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Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
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Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
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Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
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Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
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Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.
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Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.
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Entity compiled.
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Architecture behavioral of Entity serial_receiver is up to date.
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Entity (Architecture ) compiled.
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=========================================================================
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=========================================================================
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* Design Hierarchy Analysis *
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* Design Hierarchy Analysis *
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=========================================================================
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=========================================================================
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Analyzing hierarchy for entity in library (architecture ).
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Analyzing hierarchy for entity in library (architecture ).
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| Line 118... |
Line 120... |
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=========================================================================
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=========================================================================
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* HDL Analysis *
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* HDL Analysis *
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=========================================================================
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=========================================================================
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Analyzing Entity in library (Architecture ).
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Analyzing Entity in library (Architecture ).
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WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 86: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
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Entity analyzed. Unit generated.
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Entity analyzed. Unit generated.
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=========================================================================
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=========================================================================
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* HDL Synthesis *
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* HDL Synthesis *
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=========================================================================
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=========================================================================
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Performing bidirectional port resolution...
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Synthesizing Unit .
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Related source file is "E:/uart_block/hdl/iseProject/serial_receiver.vhd".
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Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Found finite state machine for signal .
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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| States | 10 |
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| States | 10 |
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| Transitions | 10 |
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| Transitions | 10 |
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| Inputs | 0 |
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| Inputs | 0 |
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| Outputs | 10 |
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| Outputs | 11 |
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| Clock | baudClk (rising_edge) |
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| Clock | baudClk (rising_edge) |
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| Reset | syncDetected (negative) |
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| Reset | syncDetected (negative) |
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| Reset type | asynchronous |
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| Reset type | asynchronous |
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| Reset State | rx_idle |
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| Reset State | bit0 |
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| Power Up State | rx_idle |
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| Power Up State | bit0 |
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| Encoding | automatic |
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| Encoding | automatic |
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| Implementation | LUT |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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Found finite state machine for signal .
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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| Line 159... |
Line 159... |
| Reset State | s0 |
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| Reset State | s0 |
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| Power Up State | s0 |
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| Power Up State | s0 |
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| Encoding | automatic |
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| Encoding | automatic |
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| Implementation | LUT |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 1-bit register for signal .
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 8-bit register for signal .
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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Found 8-bit register for signal .
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
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Found 8-bit tristate buffer for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Summary:
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Summary:
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inferred 2 Finite State Machine(s).
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inferred 2 Finite State Machine(s).
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inferred 1 D-type flip-flop(s).
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inferred 18 D-type flip-flop(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Unit synthesized.
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=========================================================================
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=========================================================================
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HDL Synthesis Report
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HDL Synthesis Report
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Macro Statistics
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Macro Statistics
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# Registers : 1
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# Registers : 11
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1-bit register : 1
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1-bit register : 10
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# Latches : 17
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8-bit register : 1
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1-bit latch : 16
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8-bit latch : 1
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# Tristates : 8
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1-bit tristate buffer : 8
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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* Advanced HDL Synthesis *
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| Line 226... |
Line 198... |
Analyzing FSM for best encoding.
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with one-hot encoding.
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Optimizing FSM on signal with one-hot encoding.
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-----------------------
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-----------------------
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State | Encoding
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State | Encoding
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-----------------------
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-----------------------
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rx_idle | 0000000001
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bit0 | 0000000001
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bit0 | 0000000010
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bit1 | 0000000010
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bit1 | 0000000100
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bit2 | 0000000100
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bit2 | 0000001000
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bit3 | 0000001000
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bit3 | 0000010000
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bit4 | 0000010000
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bit4 | 0000100000
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bit5 | 0000100000
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bit5 | 0001000000
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bit6 | 0001000000
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bit6 | 0010000000
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bit7 | 0010000000
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bit7 | 0100000000
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rx_stop | 0100000000
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rx_stop | 1000000000
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rx_idle | 1000000000
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-----------------------
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-----------------------
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Advanced HDL Synthesis Report
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Macro Statistics
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Macro Statistics
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# FSMs : 2
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# FSMs : 2
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# Registers : 1
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# Registers : 18
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Flip-Flops : 1
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Flip-Flops : 18
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# Latches : 17
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1-bit latch : 16
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8-bit latch : 1
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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* Low Level Synthesis *
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=========================================================================
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=========================================================================
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WARNING:Xst:2042 - Unit serial_receiver: 8 internal tristates are replaced by logic (pull-up yes): byteReceived<0>, byteReceived<1>, byteReceived<2>, byteReceived<3>, byteReceived<4>, byteReceived<5>, byteReceived<6>, byteReceived<7>.
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INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
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Optimizing unit ...
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Optimizing unit ...
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Mapping all equations...
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Mapping all equations...
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Building and optimizing final netlist ...
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Building and optimizing final netlist ...
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| Line 268... |
Line 237... |
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=========================================================================
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=========================================================================
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Final Register Report
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Final Register Report
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Macro Statistics
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Macro Statistics
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# Registers : 13
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# Registers : 29
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Flip-Flops : 13
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Flip-Flops : 29
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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* Partition Report *
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* Partition Report *
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| Line 298... |
Line 267... |
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Design Statistics
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Design Statistics
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# IOs : 13
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# IOs : 13
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Cell Usage :
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Cell Usage :
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# BELS : 39
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# BELS : 19
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# GND : 1
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# GND : 1
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# INV : 3
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# INV : 1
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# LUT2 : 12
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# LUT2 : 1
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# LUT3 : 8
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# LUT2_L : 1
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# LUT4 : 14
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# LUT3 : 1
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# LUT3_D : 1
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# LUT4 : 11
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# LUT4_D : 1
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# VCC : 1
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# VCC : 1
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# FlipFlops/Latches : 37
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# FlipFlops/Latches : 29
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# FDC : 11
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# FDC : 11
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# FDCE : 1
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# FDCE : 9
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# FDE : 8
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# FDP : 1
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# FDP : 1
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# LD : 17
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# LDE : 7
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# Clock Buffers : 2
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# Clock Buffers : 2
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# BUFGP : 2
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# BUFGP : 2
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# IO Buffers : 11
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# IO Buffers : 11
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# IBUF : 2
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# IBUF : 2
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# OBUF : 9
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# OBUF : 9
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| Line 323... |
Line 294... |
Device utilization summary:
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Device utilization summary:
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---------------------------
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---------------------------
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Selected Device : 3s500efg320-4
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Selected Device : 3s500efg320-4
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Number of Slices: 20 out of 4656 0%
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Number of Slices: 19 out of 4656 0%
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Number of Slice Flip Flops: 29 out of 9312 0%
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Number of Slice Flip Flops: 29 out of 9312 0%
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Number of 4 input LUTs: 37 out of 9312 0%
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Number of 4 input LUTs: 17 out of 9312 0%
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Number of IOs: 13
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Number of IOs: 13
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Number of bonded IOBs: 13 out of 232 5%
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Number of bonded IOBs: 13 out of 232 5%
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IOB Flip Flops: 8
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Number of GCLKs: 2 out of 24 8%
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Number of GCLKs: 2 out of 24 8%
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---------------------------
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---------------------------
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Partition Resource Summary:
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Partition Resource Summary:
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---------------------------
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---------------------------
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| Line 349... |
Line 319... |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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Clock Information:
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------------------
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------------------
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-----------------------------------------------------------------+--------------------------------+-------+
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-----------------------------------+------------------------+-------+
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Clock Signal | Clock buffer(FF name) | Load |
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Clock Signal | Clock buffer(FF name) | Load |
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-----------------------------------------------------------------+--------------------------------+-------+
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-----------------------------------+------------------------+-------+
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baudOverSampleClk | BUFGP | 3 |
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baudOverSampleClk | BUFGP | 3 |
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current_s_FSM_FFd8 | NONE(Mtridata_byteReceived<7>) | 7 |
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baudClk | BUFGP | 26 |
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Mtrien_byteReceived<7>_not0001(Mtrien_byteReceived<7>_not00011:O)| NONE(*)(Mtrien_byteReceived<7>)| 1 |
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-----------------------------------+------------------------+-------+
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Mtrien_byteReceived<6>_not0001(Mtrien_byteReceived<6>_not0001:O) | NONE(*)(Mtrien_byteReceived<6>)| 1 |
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Mtrien_byteReceived<5>_not0001(Mtrien_byteReceived<5>_not00011:O)| NONE(*)(Mtrien_byteReceived<5>)| 1 |
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Mtrien_byteReceived<4>_not0001(Mtrien_byteReceived<4>_not0001:O) | NONE(*)(Mtrien_byteReceived<4>)| 1 |
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Mtrien_byteReceived<3>_not0001(Mtrien_byteReceived<3>_not00011:O)| NONE(*)(Mtrien_byteReceived<3>)| 1 |
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Mtrien_byteReceived<2>_not0001(Mtrien_byteReceived<2>_not00011:O)| NONE(*)(Mtrien_byteReceived<2>)| 1 |
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Mtrien_byteReceived<1>_not0001(Mtrien_byteReceived<1>_not00011:O)| NONE(*)(Mtrien_byteReceived<1>)| 1 |
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Mtrien_byteReceived<0>_not0001(Mtrien_byteReceived<0>_not00011:O)| NONE(*)(Mtrien_byteReceived<0>)| 1 |
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current_s_FSM_FFd9 | NONE(Mtridata_byteReceived<0>) | 1 |
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baudClk | BUFGP | 10 |
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current_s_FSM_FFd1 | NONE(data_byte_0) | 8 |
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-----------------------------------------------------------------+--------------------------------+-------+
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(*) These 8 clock signal(s) are generated by combinatorial logic,
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and XST is not able to identify which are the primary clock signals.
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Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
|
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INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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Asynchronous Control Signals Information:
|
Asynchronous Control Signals Information:
|
----------------------------------------
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----------------------------------------
|
---------------------------------------------------------------+-------------------------+-------+
|
---------------------------------------------------------------+------------------------+-------+
|
Control Signal | Buffer(FF name) | Load |
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Control Signal | Buffer(FF name) | Load |
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---------------------------------------------------------------+-------------------------+-------+
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---------------------------------------------------------------+------------------------+-------+
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current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(current_s_FSM_FFd1)| 10 |
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current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(byteReceived_0) | 18 |
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rst | IBUF | 3 |
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rst | IBUF | 3 |
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---------------------------------------------------------------+-------------------------+-------+
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---------------------------------------------------------------+------------------------+-------+
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|
Timing Summary:
|
Timing Summary:
|
---------------
|
---------------
|
Speed Grade: -4
|
Speed Grade: -4
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|
|
Minimum period: 2.213ns (Maximum Frequency: 451.875MHz)
|
Minimum period: 4.853ns (Maximum Frequency: 206.058MHz)
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Minimum input arrival time before clock: 5.900ns
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Minimum input arrival time before clock: 4.569ns
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Maximum output required time after clock: 4.745ns
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Maximum output required time after clock: 4.450ns
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Maximum combinational path delay: No path found
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Maximum combinational path delay: No path found
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|
|
Timing Detail:
|
Timing Detail:
|
--------------
|
--------------
|
All values displayed in nanoseconds (ns)
|
All values displayed in nanoseconds (ns)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
|
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
|
Clock period: 2.213ns (frequency: 451.875MHz)
|
Clock period: 2.489ns (frequency: 401.768MHz)
|
Total number of paths / destination ports: 6 / 3
|
Total number of paths / destination ports: 6 / 3
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
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Delay: 2.213ns (Levels of Logic = 1)
|
Delay: 2.489ns (Levels of Logic = 1)
|
Source: filterRx_FSM_FFd1 (FF)
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Source: syncDetected (FF)
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Destination: filterRx_FSM_FFd2 (FF)
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Destination: syncDetected (FF)
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Source Clock: baudOverSampleClk rising
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Source Clock: baudOverSampleClk rising
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Destination Clock: baudOverSampleClk rising
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Destination Clock: baudOverSampleClk rising
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Data Path: filterRx_FSM_FFd1 to filterRx_FSM_FFd2
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Data Path: syncDetected to syncDetected
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Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDC:C->Q 3 0.591 0.610 filterRx_FSM_FFd1 (filterRx_FSM_FFd1)
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FDC:C->Q 10 0.591 0.886 syncDetected (syncDetected)
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LUT2:I1->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
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LUT4:I3->O 1 0.704 0.000 syncDetected_mux00001 (syncDetected_mux0000)
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FDC:D 0.308 filterRx_FSM_FFd2
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FDC:D 0.308 syncDetected
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----------------------------------------
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----------------------------------------
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Total 2.213ns (1.603ns logic, 0.610ns route)
|
Total 2.489ns (1.603ns logic, 0.886ns route)
|
(72.4% logic, 27.6% route)
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(64.4% logic, 35.6% route)
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|
|
=========================================================================
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Timing constraint: Default period analysis for Clock 'current_s_FSM_FFd8'
|
|
Clock period: 2.170ns (frequency: 460.829MHz)
|
|
Total number of paths / destination ports: 6 / 6
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|
-------------------------------------------------------------------------
|
|
Delay: 2.170ns (Levels of Logic = 1)
|
|
Source: Mtridata_byteReceived<7> (LATCH)
|
|
Destination: Mtridata_byteReceived<7> (LATCH)
|
|
Source Clock: current_s_FSM_FFd8 rising
|
|
Destination Clock: current_s_FSM_FFd8 rising
|
|
|
|
Data Path: Mtridata_byteReceived<7> to Mtridata_byteReceived<7>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
LDE:G->Q 2 0.676 0.482 Mtridata_byteReceived<7> (Mtridata_byteReceived<7>)
|
|
LUT3:I2->O 1 0.704 0.000 Mtridata_byteReceived<7>_mux00001 (Mtridata_byteReceived<7>_mux0000)
|
|
LDE:D 0.308 Mtridata_byteReceived<7>
|
|
----------------------------------------
|
|
Total 2.170ns (1.688ns logic, 0.482ns route)
|
|
(77.8% logic, 22.2% route)
|
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default period analysis for Clock 'baudClk'
|
Timing constraint: Default period analysis for Clock 'baudClk'
|
Clock period: 1.950ns (frequency: 512.821MHz)
|
Clock period: 4.853ns (frequency: 206.058MHz)
|
Total number of paths / destination ports: 9 / 9
|
Total number of paths / destination ports: 113 / 25
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Delay: 1.950ns (Levels of Logic = 0)
|
Delay: 4.853ns (Levels of Logic = 3)
|
Source: current_s_FSM_FFd10 (FF)
|
Source: current_s_FSM_FFd7 (FF)
|
Destination: current_s_FSM_FFd9 (FF)
|
Destination: data_byte_0 (FF)
|
Source Clock: baudClk rising
|
Source Clock: baudClk rising
|
Destination Clock: baudClk rising
|
Destination Clock: baudClk rising
|
|
|
Data Path: current_s_FSM_FFd10 to current_s_FSM_FFd9
|
Data Path: current_s_FSM_FFd7 to data_byte_0
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDP:C->Q 17 0.591 1.051 current_s_FSM_FFd10 (current_s_FSM_FFd10)
|
FDC:C->Q 3 0.591 0.706 current_s_FSM_FFd7 (current_s_FSM_FFd7)
|
FDC:D 0.308 current_s_FSM_FFd9
|
LUT4:I0->O 1 0.704 0.424 data_byte_mux0000<0>1_SW0 (N5)
|
|
LUT4_D:I3->O 7 0.704 0.712 data_byte_mux0000<0>1 (N01)
|
|
LUT4:I3->O 1 0.704 0.000 data_byte_mux0000<6>1 (data_byte_mux0000<6>)
|
|
FDE:D 0.308 data_byte_6
|
----------------------------------------
|
----------------------------------------
|
Total 1.950ns (0.899ns logic, 1.051ns route)
|
Total 4.853ns (3.011ns logic, 1.842ns route)
|
(46.1% logic, 53.9% route)
|
(62.0% logic, 38.0% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
|
Total number of paths / destination ports: 3 / 3
|
Total number of paths / destination ports: 3 / 3
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 3.287ns (Levels of Logic = 2)
|
Offset: 3.366ns (Levels of Logic = 2)
|
Source: serial_in (PAD)
|
Source: serial_in (PAD)
|
Destination: syncDetected (FF)
|
Destination: filterRx_FSM_FFd2 (FF)
|
Destination Clock: baudOverSampleClk rising
|
Destination Clock: baudOverSampleClk rising
|
|
|
Data Path: serial_in to syncDetected
|
Data Path: serial_in to filterRx_FSM_FFd2
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)
|
IBUF:I->O 12 1.218 1.136 serial_in_IBUF (serial_in_IBUF)
|
LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
|
LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
|
FDC:D 0.308 filterRx_FSM_FFd2
|
FDC:D 0.308 filterRx_FSM_FFd2
|
----------------------------------------
|
----------------------------------------
|
Total 3.287ns (2.230ns logic, 1.057ns route)
|
Total 3.366ns (2.230ns logic, 1.136ns route)
|
(67.8% logic, 32.2% route)
|
(66.3% logic, 33.7% route)
|
|
|
=========================================================================
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd8'
|
|
Total number of paths / destination ports: 8 / 7
|
|
-------------------------------------------------------------------------
|
|
Offset: 5.900ns (Levels of Logic = 4)
|
|
Source: serial_in (PAD)
|
|
Destination: Mtridata_byteReceived<6> (LATCH)
|
|
Destination Clock: current_s_FSM_FFd8 rising
|
|
|
|
Data Path: serial_in to Mtridata_byteReceived<6>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)
|
|
LUT3:I0->O 3 0.704 0.610 Mtridata_byteReceived<6>_mux000021 (N8)
|
|
LUT3:I1->O 1 0.704 0.595 Mtridata_byteReceived<6>_mux0000_SW0 (N17)
|
|
LUT4:I0->O 1 0.704 0.000 Mtridata_byteReceived<6>_mux0000 (Mtridata_byteReceived<6>_mux0000)
|
|
LDE:D 0.308 Mtridata_byteReceived<6>
|
|
----------------------------------------
|
|
Total 5.900ns (3.638ns logic, 2.262ns route)
|
|
(61.7% logic, 38.3% route)
|
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd9'
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudClk'
|
Total number of paths / destination ports: 1 / 1
|
Total number of paths / destination ports: 9 / 9
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 2.408ns (Levels of Logic = 1)
|
Offset: 4.569ns (Levels of Logic = 3)
|
Source: serial_in (PAD)
|
Source: serial_in (PAD)
|
Destination: Mtridata_byteReceived<0> (LATCH)
|
Destination: data_byte_7 (FF)
|
Destination Clock: current_s_FSM_FFd9 falling
|
Destination Clock: baudClk rising
|
|
|
Data Path: serial_in to Mtridata_byteReceived<0>
|
Data Path: serial_in to data_byte_7
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
IBUF:I->O 10 1.218 0.882 serial_in_IBUF (serial_in_IBUF)
|
IBUF:I->O 12 1.218 1.136 serial_in_IBUF (serial_in_IBUF)
|
LD:D 0.308 Mtridata_byteReceived<0>
|
LUT4:I0->O 1 0.704 0.499 data_byte_mux0000<7>_SW0 (N3)
|
|
LUT3:I1->O 1 0.704 0.000 data_byte_mux0000<7> (data_byte_mux0000<7>)
|
|
FDE:D 0.308 data_byte_7
|
----------------------------------------
|
----------------------------------------
|
Total 2.408ns (1.526ns logic, 0.882ns route)
|
Total 4.569ns (2.934ns logic, 1.635ns route)
|
(63.4% logic, 36.6% route)
|
(64.2% logic, 35.8% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
|
Total number of paths / destination ports: 1 / 1
|
Total number of paths / destination ports: 9 / 9
|
-------------------------------------------------------------------------
|
-------------------------------------------------------------------------
|
Offset: 4.745ns (Levels of Logic = 1)
|
Offset: 4.450ns (Levels of Logic = 1)
|
Source: current_s_FSM_FFd1 (FF)
|
Source: current_s_FSM_FFd1 (FF)
|
Destination: data_ready (PAD)
|
Destination: data_ready (PAD)
|
Source Clock: baudClk rising
|
Source Clock: baudClk rising
|
|
|
Data Path: current_s_FSM_FFd1 to data_ready
|
Data Path: current_s_FSM_FFd1 to data_ready
|
Gate Net
|
Gate Net
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
---------------------------------------- ------------
|
---------------------------------------- ------------
|
FDCE:C->Q 10 0.591 0.882 current_s_FSM_FFd1 (current_s_FSM_FFd1)
|
FDCE:C->Q 4 0.591 0.587 current_s_FSM_FFd1 (current_s_FSM_FFd1)
|
OBUF:I->O 3.272 data_ready_OBUF (data_ready)
|
OBUF:I->O 3.272 data_ready_OBUF (data_ready)
|
----------------------------------------
|
----------------------------------------
|
Total 4.745ns (3.863ns logic, 0.882ns route)
|
Total 4.450ns (3.863ns logic, 0.587ns route)
|
(81.4% logic, 18.6% route)
|
(86.8% logic, 13.2% route)
|
|
|
=========================================================================
|
=========================================================================
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd1'
|
|
Total number of paths / destination ports: 8 / 8
|
|
-------------------------------------------------------------------------
|
|
Offset: 4.368ns (Levels of Logic = 1)
|
|
Source: data_byte_7 (LATCH)
|
|
Destination: data_byte<7> (PAD)
|
|
Source Clock: current_s_FSM_FFd1 falling
|
|
|
|
Data Path: data_byte_7 to data_byte<7>
|
|
Gate Net
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
---------------------------------------- ------------
|
|
LD:G->Q 1 0.676 0.420 data_byte_7 (data_byte_7)
|
|
OBUF:I->O 3.272 data_byte_7_OBUF (data_byte<7>)
|
|
----------------------------------------
|
|
Total 4.368ns (3.948ns logic, 0.420ns route)
|
|
(90.4% logic, 9.6% route)
|
|
|
|
=========================================================================
|
|
|
|
|
Total REAL time to Xst completion: 5.00 secs
|
Total REAL time to Xst completion: 3.00 secs
|
Total CPU time to Xst completion: 4.59 secs
|
Total CPU time to Xst completion: 3.32 secs
|
|
|
|
-->
|
-->
|
|
|
Total memory usage is 258164 kilobytes
|
|
|
Total memory usage is 164420 kilobytes
|
|
|
Number of errors : 0 ( 0 filtered)
|
Number of errors : 0 ( 0 filtered)
|
Number of warnings : 19 ( 0 filtered)
|
Number of warnings : 0 ( 0 filtered)
|
Number of infos : 9 ( 0 filtered)
|
Number of infos : 1 ( 0 filtered)
|
|
|
