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signal current_s,next_s: rxStates;
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signal current_s,next_s: rxStates;
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signal filterRx : rxFilterStates;
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signal filterRx : rxFilterStates;
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signal syncDetected : std_logic;
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signal syncDetected : std_logic;
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begin
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begin
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-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC
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-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
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process (rst, baudOverSampleClk, serial_in, current_s)
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process (rst, baudOverSampleClk, serial_in, current_s)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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filterRx <= s0;
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filterRx <= s0;
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syncDetected <= '0';
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syncDetected <= '0';
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elsif rising_edge(baudOverSampleClk) then
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elsif rising_edge(baudOverSampleClk) then
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case filterRx is
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case filterRx is
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when s0 =>
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when s0 =>
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syncDetected <= '0';
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syncDetected <= '0';
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-- Spike down detected, verify if it's valid for at least 3 cycles
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-- Spike down detected, verify if it's valid for at least 3 cycles
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-- We shoose a little bit on the end to enforce the baud clk to sample
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-- the data at the right time... iE we're going to start sampling when
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-- the stop has been detected and we already for some of the first bit
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-- signal
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s1;
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filterRx <= s1;
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else
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else
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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