| Line 15... |
Line 15... |
data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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end serial_receiver;
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end serial_receiver;
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architecture Behavioral of serial_receiver is
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architecture Behavioral of serial_receiver is
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signal current_s,next_s: rxStates;
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signal current_s: rxStates;
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signal filterRx : rxFilterStates;
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signal filterRx : rxFilterStates;
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signal syncDetected : std_logic;
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signal syncDetected : std_logic;
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begin
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begin
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-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
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-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
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| Line 67... |
Line 67... |
filterRx <= s3;
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filterRx <= s3;
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syncDetected <= '1';
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syncDetected <= '1';
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end if;
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end if;
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-- Reset out sync detector when finished to receive a byte
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-- Reset out sync detector when finished to receive a byte
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if current_s = rx_stop then
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if current_s = rx_idle then
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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|
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-- Next state logic for rx Receiver (On this case our reset is the syncDetected signal
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-- Process to handle the serial receive (On this case our reset is the syncDetected signal
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-- Always include all of your signals on the sensivity list!! (Even if the simulation is already ok)
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process (syncDetected, baudClk, serial_in)
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process (syncDetected, baudClk, serial_in)
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variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
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begin
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begin
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if syncDetected = '0' then
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if syncDetected = '0' then
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current_s <= rx_idle;
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current_s <= bit0;
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data_ready <= '0';
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byteReceived := (others => '0');
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elsif rising_edge(baudClk) then
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elsif rising_edge(baudClk) then
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current_s <= next_s;
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end if;
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end process;
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|
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-- Process to handle the serial receive
|
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process (current_s, serial_in)
|
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variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
|
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begin
|
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case current_s is
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case current_s is
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when rx_idle =>
|
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data_ready <= '0';
|
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byteReceived := (others => 'Z');
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next_s <= bit0;
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|
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when bit0 =>
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when bit0 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(0) := serial_in;
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byteReceived(0) := serial_in;
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next_s <= bit1;
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current_s <= bit1;
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|
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when bit1 =>
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when bit1 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(1) := serial_in;
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byteReceived(1) := serial_in;
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next_s <= bit2;
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current_s <= bit2;
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|
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when bit2 =>
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when bit2 =>
|
data_ready <= '0';
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data_ready <= '0';
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byteReceived(2) := serial_in;
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byteReceived(2) := serial_in;
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next_s <= bit3;
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current_s <= bit3;
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|
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when bit3 =>
|
when bit3 =>
|
data_ready <= '0';
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data_ready <= '0';
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byteReceived(3) := serial_in;
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byteReceived(3) := serial_in;
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next_s <= bit4;
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current_s <= bit4;
|
|
|
when bit4 =>
|
when bit4 =>
|
data_ready <= '0';
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data_ready <= '0';
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byteReceived(4) := serial_in;
|
byteReceived(4) := serial_in;
|
next_s <= bit5;
|
current_s <= bit5;
|
|
|
when bit5 =>
|
when bit5 =>
|
data_ready <= '0';
|
data_ready <= '0';
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byteReceived(5) := serial_in;
|
byteReceived(5) := serial_in;
|
next_s <= bit6;
|
current_s <= bit6;
|
|
|
when bit6 =>
|
when bit6 =>
|
data_ready <= '0';
|
data_ready <= '0';
|
byteReceived(6) := serial_in;
|
byteReceived(6) := serial_in;
|
next_s <= bit7;
|
current_s <= bit7;
|
|
|
when bit7 =>
|
when bit7 =>
|
data_ready <= '0';
|
data_ready <= '0';
|
byteReceived(7) := serial_in;
|
byteReceived(7) := serial_in;
|
data_byte <= byteReceived;
|
data_byte <= byteReceived;
|
next_s <= rx_stop;
|
current_s <= rx_stop;
|
|
|
when rx_stop =>
|
when rx_stop =>
|
data_ready <= '1';
|
data_ready <= '1';
|
next_s <= rx_stop;
|
data_byte <= byteReceived;
|
end case;
|
current_s <= rx_idle;
|
|
|
|
when rx_idle =>
|
|
data_ready <= '1';
|
|
data_byte <= byteReceived;
|
|
current_s <= rx_idle;
|
|
|
|
end case;
|
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
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No newline at end of file
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No newline at end of file
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