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--! Data receiver
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--! @file
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--! http://www.fpga4fun.com/SerialInterface.html
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--! @brief Serial receiver http://www.fpga4fun.com/SerialInterface.html
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity serial_receiver is
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entity serial_receiver is
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Port (
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Port (
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rst : in STD_LOGIC;
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rst : in STD_LOGIC; --! Reset input
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baudOverSampleClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
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serial_in : in STD_LOGIC;
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serial_in : in STD_LOGIC; --! Uart serial input
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data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC; --! Data received and ready to be read
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
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end serial_receiver;
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end serial_receiver;
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--! @brief Serial receiver http://www.fpga4fun.com/SerialInterface.html
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--! @details Implement block that create a byte from the serial stream of data.
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architecture Behavioral of serial_receiver is
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architecture Behavioral of serial_receiver is
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signal current_s: rxStates;
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signal current_s: rxStates;
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signal filterRx : rxFilterStates;
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signal filterRx : rxFilterStates;
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signal syncDetected : std_logic;
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signal syncDetected : std_logic;
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begin
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begin
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-- First we need to oversample(4x baud rate) out serial channel to syncronize with the PC
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-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC (By detecting the start bit)
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process (rst, baudOverSampleClk, serial_in, current_s)
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process (rst, baudOverSampleClk, serial_in, current_s)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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filterRx <= s0;
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filterRx <= s0;
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syncDetected <= '0';
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syncDetected <= '0';
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elsif rising_edge(baudOverSampleClk) then
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elsif rising_edge(baudOverSampleClk) then
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case filterRx is
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case filterRx is
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when s0 =>
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when s0 =>
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syncDetected <= '0';
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syncDetected <= '0';
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-- Spike down detected, verify if it's valid for at least 3 cycles
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-- Spike down detected, verify if it's valid for at least 4 cycles
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-- We shoose a little bit on the end to enforce the baud clk to sample
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-- the data at the right time... iE we're going to start sampling when
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-- the stop has been detected and we already for some of the first bit
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-- signal
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s1;
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filterRx <= s1;
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else
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else
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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