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Release 13.4 - xst O.87xd (nt64)
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Release 13.4 - xst O.87xd (lin)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.22 secs
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Total CPU time to Xst completion: 0.06 secs
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--> Parameter xsthdpdir set to xst
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.22 secs
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Total CPU time to Xst completion: 0.06 secs
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--> Reading design: serial_transmitter.prj
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-->
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Reading design: serial_transmitter.prj
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TABLE OF CONTENTS
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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1) Synthesis Options Summary
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2) HDL Compilation
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2) HDL Compilation
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3) Design Hierarchy Analysis
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3) Design Hierarchy Analysis
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=========================================================================
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=========================================================================
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* HDL Compilation *
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* HDL Compilation *
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=========================================================================
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=========================================================================
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Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
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Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
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Package compiled.
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Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
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Package body compiled.
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Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
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Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
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Architecture behavioral of Entity serial_transmitter is up to date.
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Architecture behavioral of Entity serial_transmitter is up to date.
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=========================================================================
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=========================================================================
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* Design Hierarchy Analysis *
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* Design Hierarchy Analysis *
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=========================================================================
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=========================================================================
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=========================================================================
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=========================================================================
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Performing bidirectional port resolution...
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Synthesizing Unit .
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Related source file is "E:/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Found finite state machine for signal .
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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| States | 12 |
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| States | 12 |
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| Transitions | 12 |
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| Transitions | 12 |
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| Inputs | 0 |
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| Inputs | 0 |
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(77.3% logic, 22.7% route)
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(77.3% logic, 22.7% route)
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=========================================================================
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=========================================================================
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Total REAL time to Xst completion: 5.00 secs
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Total REAL time to Xst completion: 4.00 secs
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Total CPU time to Xst completion: 5.00 secs
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Total CPU time to Xst completion: 4.47 secs
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-->
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-->
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Total memory usage is 255476 kilobytes
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Total memory usage is 163788 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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