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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_transmitter.syr] - Diff between revs 2 and 15

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Rev 2 Rev 15
Line 1... Line 1...
Release 13.4 - xst O.87xd (nt64)
Release 13.4 - xst O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
-->
 
Parameter TMPDIR set to xst/projnav.tmp
 
 
 
 
Total REAL time to Xst completion: 0.00 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.22 secs
Total CPU time to Xst completion: 0.06 secs
 
 
--> Parameter xsthdpdir set to xst
-->
 
Parameter xsthdpdir set to xst
 
 
 
 
Total REAL time to Xst completion: 0.00 secs
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.22 secs
Total CPU time to Xst completion: 0.06 secs
 
 
--> Reading design: serial_transmitter.prj
-->
 
Reading design: serial_transmitter.prj
 
 
TABLE OF CONTENTS
TABLE OF CONTENTS
  1) Synthesis Options Summary
  1) Synthesis Options Summary
  2) HDL Compilation
  2) HDL Compilation
  3) Design Hierarchy Analysis
  3) Design Hierarchy Analysis
Line 102... Line 105...
 
 
 
 
=========================================================================
=========================================================================
*                          HDL Compilation                              *
*                          HDL Compilation                              *
=========================================================================
=========================================================================
Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Package  compiled.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Package body  compiled.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
 
Architecture behavioral of Entity serial_transmitter is up to date.
Architecture behavioral of Entity serial_transmitter is up to date.
 
 
=========================================================================
=========================================================================
*                     Design Hierarchy Analysis                         *
*                     Design Hierarchy Analysis                         *
=========================================================================
=========================================================================
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=========================================================================
=========================================================================
 
 
Performing bidirectional port resolution...
Performing bidirectional port resolution...
 
 
Synthesizing Unit .
Synthesizing Unit .
    Related source file is "E:/uart_block/hdl/iseProject/serial_transmitter.vhd".
    Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
    Found finite state machine  for signal .
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | States             | 12                                             |
    | Transitions        | 12                                             |
    | Transitions        | 12                                             |
    | Inputs             | 0                                              |
    | Inputs             | 0                                              |
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                                       (77.3% logic, 22.7% route)
                                       (77.3% logic, 22.7% route)
 
 
=========================================================================
=========================================================================
 
 
 
 
Total REAL time to Xst completion: 5.00 secs
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.47 secs
 
 
-->
-->
 
 
Total memory usage is 255476 kilobytes
 
 
Total memory usage is 163788 kilobytes
 
 
Number of errors   :    0 (   0 filtered)
Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 
 

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