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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_transmitter.vhd] - Diff between revs 2 and 37
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--! Data transmitter
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--! @file
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--! http://www.fpga4fun.com/SerialInterface.html
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--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity serial_transmitter is
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entity serial_transmitter is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Reset input
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baudClk : in STD_LOGIC;
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baudClk : in STD_LOGIC; --! Baud rate clock input
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_sent : out STD_LOGIC;
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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serial_out : out STD_LOGIC);
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serial_out : out STD_LOGIC); --! Uart serial output
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end serial_transmitter;
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end serial_transmitter;
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--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
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--! @details Implement block that serialize the "data_byte" signal on a stream of bits clocked out by "baudClk"
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architecture Behavioral of serial_transmitter is
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architecture Behavioral of serial_transmitter is
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signal current_s,next_s: txStates;
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signal current_s,next_s: txStates;
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begin
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begin
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-- Next state process
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-- Next state process
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