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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 9 and 11
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ENTITY testBaud_generator IS
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ENTITY testBaud_generator IS
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END testBaud_generator;
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END testBaud_generator;
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ARCHITECTURE behavior OF testBaud_generator IS
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ARCHITECTURE behavior OF testBaud_generator IS
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COMPONENT baud_generator
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COMPONENT baud_generator
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PORT(
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PORT(
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rst : IN std_logic;
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rst : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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baud_oversample : out std_logic;
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baud : OUT std_logic
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baud : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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--Outputs
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--Outputs
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signal baud : std_logic;
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signal baud : std_logic;
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signal baud_oversample : std_logic;
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-- Clock period definitions (1.8432MHz)
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-- Clock period definitions (1.8432MHz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: baud_generator PORT MAP (
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uut: baud_generator PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cycle_wait => cycle_wait,
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cycle_wait => cycle_wait,
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baud_oversample => baud_oversample,
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baud => baud
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baud => baud
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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