URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 9 and 11
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 9 |
Rev 11 |
| Line 10... |
Line 10... |
ENTITY testBaud_generator IS
|
ENTITY testBaud_generator IS
|
END testBaud_generator;
|
END testBaud_generator;
|
|
|
ARCHITECTURE behavior OF testBaud_generator IS
|
ARCHITECTURE behavior OF testBaud_generator IS
|
|
|
|
|
|
|
COMPONENT baud_generator
|
COMPONENT baud_generator
|
PORT(
|
PORT(
|
rst : IN std_logic;
|
rst : IN std_logic;
|
clk : IN std_logic;
|
clk : IN std_logic;
|
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
|
baud_oversample : out std_logic;
|
baud : OUT std_logic
|
baud : OUT std_logic
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
|
|
|
|
|
| Line 29... |
Line 28... |
signal clk : std_logic := '0';
|
signal clk : std_logic := '0';
|
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
|
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
|
|
|
--Outputs
|
--Outputs
|
signal baud : std_logic;
|
signal baud : std_logic;
|
|
signal baud_oversample : std_logic;
|
|
|
-- Clock period definitions (1.8432MHz)
|
-- Clock period definitions (1.8432MHz)
|
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
|
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
|
|
|
BEGIN
|
BEGIN
|
| Line 40... |
Line 40... |
-- Instantiate the Unit Under Test (UUT)
|
-- Instantiate the Unit Under Test (UUT)
|
uut: baud_generator PORT MAP (
|
uut: baud_generator PORT MAP (
|
rst => rst,
|
rst => rst,
|
clk => clk,
|
clk => clk,
|
cycle_wait => cycle_wait,
|
cycle_wait => cycle_wait,
|
|
baud_oversample => baud_oversample,
|
baud => baud
|
baud => baud
|
);
|
);
|
|
|
-- Clock process definitions
|
-- Clock process definitions
|
clk_process :process
|
clk_process :process
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.