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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 36 and 37
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Rev 37 |
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END testBaud_generator;
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END testBaud_generator;
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ARCHITECTURE behavior OF testBaud_generator IS
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ARCHITECTURE behavior OF testBaud_generator IS
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COMPONENT baud_generator
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COMPONENT baud_generator
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PORT(
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Port ( rst : in STD_LOGIC; --! Reset Input
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rst : IN std_logic;
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clk : in STD_LOGIC; --! Clock input
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clk : IN std_logic;
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
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baud_oversample : out std_logic;
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baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
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baud : OUT std_logic
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal clk : std_logic := '0';
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signal clk : std_logic := '0'; --! Signal to connect with UUT
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal baud : std_logic;
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signal baud : std_logic; --! Signal to connect with UUT
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signal baud_oversample : std_logic;
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signal baud_oversample : std_logic; --! Signal to connect with UUT
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-- Clock period definitions (1.8432MHz)
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-- Clock period definitions (1.8432MHz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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