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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 6 and 8
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| Rev 6 |
Rev 8 |
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Line 30... |
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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--Outputs
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--Outputs
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signal baud : std_logic;
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signal baud : std_logic;
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-- Clock period definitions
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-- Clock period definitions (1.8432MHz)
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constant clk_period : time := 10 ns;
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constant clk_period : time := 5.43 us;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: baud_generator PORT MAP (
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uut: baud_generator PORT MAP (
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Line 58... |
-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- Test the baud generator waiting for 10 clock cycles
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-- Test the baud generator waiting for 10 clock cycles
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rst <= '1';
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rst <= '1';
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cycle_wait <= conv_std_logic_vector(2, (nBitsLarge));
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cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
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wait for 10 ns;
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wait for 10 us;
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rst <= '0';
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rst <= '0';
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wait for clk_period*100;
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wait for clk_period*100;
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-- Stop Simulation
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-- Stop Simulation
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