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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Diff between revs 8 and 9

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Rev 8 Rev 9
Line 31... Line 31... 
 
 
 
 
        --Outputs
 
        --Outputs
 
   signal baud : std_logic;
 
   signal baud : std_logic;
 
 
 
 
 
   -- Clock period definitions (1.8432MHz)
 
   -- Clock period definitions (1.8432MHz)
 
   constant clk_period : time := 5.43 us;
 
   constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
 
 
 
 
 
BEGIN
 
BEGIN
 
 
 
 
 
        -- Instantiate the Unit Under Test (UUT)
 
        -- Instantiate the Unit Under Test (UUT)
 
   uut: baud_generator PORT MAP (
 
   uut: baud_generator PORT MAP (
Line 56... Line 56... 
 
 
 
 
 
 
 
 
   -- Stimulus process
 
   -- Stimulus process
 
   stim_proc: process
 
   stim_proc: process
 
   begin
 
   begin
 
      -- Test the baud generator waiting for 10 clock cycles
 
      -- Test the baud generator waiting for 16 clock cycles for 1.8432MHz clock
 
                rst <= '1';
 
                rst <= '1';
 
                cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
 
                cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
 
      wait for 10 us;
 
      wait for 2 ns;
 
                rst <= '0';
 
                rst <= '0';
 
 
 
 
 
      wait for clk_period*100;
 
      wait for clk_period*300;
 
 
 
 
 
      -- Stop Simulation
 
      -- Stop Simulation
 
                assert false report "NONE. End of simulation." severity failure;
 
                assert false report "NONE. End of simulation." severity failure;
 
 
 
 
 
      wait;
 
      wait;

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