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ARCHITECTURE behavior OF testDivisor IS
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ARCHITECTURE behavior OF testDivisor IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT divisor
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COMPONENT divisor
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PORT(
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Port ( rst : in STD_LOGIC; --! Reset input
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rst : IN std_logic;
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clk : in STD_LOGIC; --! Clock input
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clk : IN std_logic;
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Division result (32 bits)
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quotient : OUT std_logic_vector((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Reminder result (32 bits)
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reminder : OUT std_logic_vector((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Numerator (32 bits)
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numerator : IN std_logic_vector((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! "Divide by" number (32 bits)
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divident : IN std_logic_vector((nBitsLarge-1) downto 0);
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done : out STD_LOGIC);
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done : OUT std_logic
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal clk : std_logic := '0';
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signal clk : std_logic := '0'; --! Signal to connect with UUT
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signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal quotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal quotient : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal reminder : std_logic_vector((nBitsLarge-1) downto 0);
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signal reminder : std_logic_vector((nBitsLarge-1) downto 0); --! Signal to connect with UUT
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signal done : std_logic;
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signal done : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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