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Line 13... |
-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_receiver
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COMPONENT serial_receiver
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PORT(
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PORT(
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rst : IN std_logic;
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rst : IN std_logic;
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baudClk : IN std_logic;
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baudOverSampleClk : IN std_logic;
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baudOverSampleClk : IN std_logic;
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serial_in : IN std_logic;
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serial_in : IN std_logic;
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data_ready : OUT std_logic;
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data_ready : OUT std_logic;
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data_byte : OUT std_logic_vector((nBits-1) downto 0)
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data_byte : OUT std_logic_vector((nBits-1) downto 0)
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);
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);
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Line 33... |
signal data_ready : std_logic;
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signal data_ready : std_logic;
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signal data_byte : std_logic_vector((nBits-1) downto 0);
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signal data_byte : std_logic_vector((nBits-1) downto 0);
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-- Clock period definitions
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-- Clock period definitions
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constant baudClk_period : time := 8.6805 us;
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constant baudClk_period : time := 8.6805 us;
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constant baudOverSampleClk_period : time := 1 us;
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constant baudOverSampleClk_period : time :=1.085 us;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: serial_receiver PORT MAP (
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uut: serial_receiver PORT MAP (
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rst => rst,
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rst => rst,
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baudClk => baudClk,
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baudOverSampleClk => baudOverSampleClk,
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baudOverSampleClk => baudOverSampleClk,
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serial_in => serial_in,
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serial_in => serial_in,
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data_ready => data_ready,
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data_ready => data_ready,
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data_byte => data_byte
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data_byte => data_byte
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);
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);
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