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ARCHITECTURE behavior OF testSerial_receiver IS
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ARCHITECTURE behavior OF testSerial_receiver IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_receiver
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COMPONENT serial_receiver
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PORT(
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Port (
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rst : IN std_logic;
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rst : in STD_LOGIC; --! Reset input
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baudOverSampleClk : IN std_logic;
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baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
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serial_in : IN std_logic;
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serial_in : in STD_LOGIC; --! Uart serial input
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data_ready : OUT std_logic;
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data_ready : out STD_LOGIC; --! Data received and ready to be read
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data_byte : OUT std_logic_vector((nBits-1) downto 0)
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal baudClk : std_logic := '0';
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signal baudClk : std_logic := '0'; --! Signal to connect with UUT
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signal baudOverSampleClk : std_logic := '0';
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signal baudOverSampleClk : std_logic := '0'; --! Signal to connect with UUT
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signal serial_in : std_logic := '0';
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signal serial_in : std_logic := '0'; --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal data_ready : std_logic;
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signal data_ready : std_logic; --! Signal to connect with UUT
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signal data_byte : std_logic_vector((nBits-1) downto 0);
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signal data_byte : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
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-- Clock period definitions
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-- Clock period definitions
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constant baudClk_period : time := 8.6805 us;
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constant baudClk_period : time := 8.6805 us;
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constant baudOverSampleClk_period : time :=1.085 us;
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constant baudOverSampleClk_period : time :=1.085 us;
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