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--! Test serial_receiver module
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--! @file
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--! @brief Test serial_receiver module module
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testSerial_receiver IS
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ENTITY testSerial_receiver IS
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END testSerial_receiver;
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END testSerial_receiver;
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--! @brief Test serial_receiver module module
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--! @details Receive some simulated byte stream and verify received values
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ARCHITECTURE behavior OF testSerial_receiver IS
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ARCHITECTURE behavior OF testSerial_receiver IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_receiver
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COMPONENT serial_receiver
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period;
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wait for baudClk_period;
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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---wait until data_ready = '1';
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assert data_byte = X"C4" report "Wrong result... expected 0xC4" severity failure;
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wait for baudClk_period * 8;
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wait for baudClk_period * 8;
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-- Receive 0x55 value (01010101)
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-- Receive 0x55 value (01010101)
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-- Start bit here
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-- Start bit here
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serial_in <= '0';
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serial_in <= '0';
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wait for baudClk_period;
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wait for baudClk_period;
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait for baudClk_period * 1;
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wait for baudClk_period * 1;
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---wait until data_ready = '1';
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assert data_byte = X"55" report "Wrong result... expected 0x55" severity failure;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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