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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testSerial_transmitter.vhd] - Diff between revs 36 and 37
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Rev 37 |
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ARCHITECTURE behavior OF testSerial_transmitter IS
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ARCHITECTURE behavior OF testSerial_transmitter IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_transmitter
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COMPONENT serial_transmitter
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PORT(
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Port ( rst : in STD_LOGIC; --! Reset input
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rst : IN std_logic;
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baudClk : in STD_LOGIC; --! Baud rate clock input
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baudClk : IN std_logic;
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_byte : IN std_logic_vector(7 downto 0);
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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data_sent : OUT std_logic;
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serial_out : out STD_LOGIC); --! Uart serial output
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serial_out : OUT std_logic
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal baudClk : std_logic := '0';
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signal baudClk : std_logic := '0'; --! Signal to connect with UUT
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signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
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signal data_byte : std_logic_vector(7 downto 0) := (others => '0'); --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal data_sent : std_logic;
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signal data_sent : std_logic; --! Signal to connect with UUT
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signal serial_out : std_logic;
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signal serial_out : std_logic; --! Signal to connect with UUT
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-- Clock period definitions
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-- Clock period definitions
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constant baudClk_period : time := 10 ns;
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constant baudClk_period : time := 10 ns;
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BEGIN
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BEGIN
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