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--! Test serial_transmitter module
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--! @file
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--! @brief Test serial_transmitter module
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testSerial_transmitter IS
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ENTITY testSerial_transmitter IS
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END testSerial_transmitter;
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END testSerial_transmitter;
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--! @brief Test serial_transmitter module
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--! @details Just send the date over the serial_out and analyse the results
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ARCHITECTURE behavior OF testSerial_transmitter IS
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ARCHITECTURE behavior OF testSerial_transmitter IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT serial_transmitter
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COMPONENT serial_transmitter
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rst <= '1';
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rst <= '1';
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data_byte <= "01010101";
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data_byte <= "01010101";
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wait for 50 ns;
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wait for 50 ns;
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rst <= '0';
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rst <= '0';
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-- Test serial data...
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wait until rising_edge(baudClk); -- Start bit
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wait for 1 ns;
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assert serial_out = '0' report "Invalid value " severity failure;
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for numBit in 0 to 7 loop
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wait until rising_edge(baudClk);
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wait for 1 ns;
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-- The image attribute convert a typed value into a string
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report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
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assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
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end loop;
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wait until data_sent = '1';
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wait until data_sent = '1';
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wait for baudClk_period*3;
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wait for baudClk_period*3;
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-- Prepare the data to be sent
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-- Prepare the data to be sent
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rst <= '1';
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rst <= '1';
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data_byte <= "11000100";
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data_byte <= "11000100";
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wait for 50 ns;
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wait for 50 ns;
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rst <= '0';
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rst <= '0';
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-- Test serial data...
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wait until rising_edge(baudClk); -- Start bit
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wait for 1 ns;
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assert serial_out = '0' report "Invalid value " severity failure;
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for numBit in 0 to (data_byte'LENGTH-1) loop
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-- Wait for the clock rising edge
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wait until rising_edge(baudClk);
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wait for 1 ns;
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report "Testing bit:" & integer'image(numBit) & " value " & std_logic'image(serial_out);
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assert serial_out = data_byte(numBit) report "Invalid value on bit:" severity failure;
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end loop;
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wait until data_sent = '1';
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wait until data_sent = '1';
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wait for baudClk_period*3;
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wait for baudClk_period*3;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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