URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_communication_block.vhd] - Diff between revs 32 and 36

Rev 32	Rev 36
Line 45...	Line 45...
`-- Clock period definitions`	`-- Clock period definitions`
`constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)`	`constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`--! Instantiate the Unit Under Test (UUT)`
`uut: uart_communication_blocks PORT MAP (`	`uut: uart_communication_blocks PORT MAP (`
`rst => rst,`	`rst => rst,`
`clk => clk,`	`clk => clk,`
`cycle_wait_baud => cycle_wait_baud,`	`cycle_wait_baud => cycle_wait_baud,`
`byte_tx => byte_tx,`	`byte_tx => byte_tx,`