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ARCHITECTURE behavior OF testUart_communication_block IS
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ARCHITECTURE behavior OF testUart_communication_block IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT uart_communication_blocks
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COMPONENT uart_communication_blocks
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Global reset
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Global clock
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
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cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0); --! Number of cycles to wait in order to generate desired baud
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to transmit
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
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byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to receive
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data_sent_tx : out STD_LOGIC;
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data_sent_tx : out STD_LOGIC; --! Indicate that byte has been sent
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data_received_rx : out STD_LOGIC;
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data_received_rx : out STD_LOGIC; --! Indicate that we got a byte
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serial_out : out std_logic;
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serial_out : out std_logic; --! Uart serial out
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serial_in : in std_logic;
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serial_in : in std_logic; --! Uart serial in
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start_tx : in STD_LOGIC);
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start_tx : in STD_LOGIC); --! Initiate transmission
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Signal to connect with UUT
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signal clk : std_logic := '0';
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signal clk : std_logic := '0'; --! Signal to connect with UUT
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signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');
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signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0'); --! Signal to connect with UUT
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signal serial_in : std_logic := '0';
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signal serial_in : std_logic := '0'; --! Signal to connect with UUT
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signal start_tx : std_logic := '0';
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signal start_tx : std_logic := '0'; --! Signal to connect with UUT
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--Outputs
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--Outputs
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signal byte_rx : std_logic_vector((nBits-1) downto 0);
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signal byte_rx : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT
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signal data_sent_tx : std_logic;
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signal data_sent_tx : std_logic; --! Signal to connect with UUT
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signal data_received_rx : std_logic;
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signal data_received_rx : std_logic; --! Signal to connect with UUT
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signal serial_out : std_logic;
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signal serial_out : std_logic; --! Signal to connect with UUT
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
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constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
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BEGIN
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BEGIN
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