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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_control.vhd] - Diff between revs 14 and 21
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| Rev 14 |
Rev 21 |
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Line 51... |
signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
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signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
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signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
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signal data_byte_tx : std_logic_vector((nBits-1) downto 0);
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 2 ns; -- 2ns (50Mhz)
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constant clk_period : time := 20 ns; -- 20ns (50Mhz)
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: uart_control PORT MAP (
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uut: uart_control PORT MAP (
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