URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_control.vhd] - Diff between revs 14 and 21

Rev 14	Rev 21
Line 51...	Line 51...
`signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);`	`signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);`
`signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);`	`signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);`
`signal data_byte_tx : std_logic_vector((nBits-1) downto 0);`	`signal data_byte_tx : std_logic_vector((nBits-1) downto 0);`

`-- Clock period definitions`	`-- Clock period definitions`
`constant clk_period : time := 2 ns; -- 2ns (50Mhz)`	`constant clk_period : time := 20 ns; -- 20ns (50Mhz)`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`-- Instantiate the Unit Under Test (UUT)`
`uut: uart_control PORT MAP (`	`uut: uart_control PORT MAP (`