URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_control.vhd] - Diff between revs 21 and 22

Rev 21	Rev 22
Line 88...	Line 88...

`-- Stimulus process`	`-- Stimulus process`
`stim_proc: process`	`stim_proc: process`
`begin`	`begin`
`rst <= '1';`	`rst <= '1';`
`wait for 1 ns;`	`start <= '0';`
	`wait for clk_period;`
`rst <= '0';`	`rst <= '0';`
`wait for clk_period*3;`	`wait for clk_period;`

`-- Configure the clock...`	`-- Configure the clock...`
`reg_addr <= "00";`	`reg_addr <= "00";`
`WE <= '1';`	`WE <= '1';`
`start <= '1';`	`start <= '1';`
Line 120...	Line 121...
`-- Ask to send some data...(0x55)`	`-- Ask to send some data...(0x55)`
`reg_addr <= "10";`	`reg_addr <= "10";`
`WE <= '1';`	`WE <= '1';`
`start <= '1';`	`start <= '1';`
`DAT_I <= x"00000055";`	`DAT_I <= x"00000055";`
`wait for clk_period*10; -- No point to use wait until because we're not connected to the comm block yet`	`wait until done = '1';`
	`WE <= '0';`
	`start <= '0';`
	`reg_addr <= (others => 'U');`
	`wait for clk_period;`

	`-- Ask to read some data...`
	`reg_addr <= "11";`
	`WE <= '0';`
	`start <= '1';`
	`wait until done = '1';`
	`start <= '0';`
	`wait for clk_period*10;`

`-- Stop Simulation`	`-- Stop Simulation`
`assert false report "NONE. End of simulation." severity failure;`	`assert false report "NONE. End of simulation." severity failure;`
`end process;`	`end process;`