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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 43... Line 43... 
   signal DAT_O0 : std_logic_vector(31 downto 0);
 
   signal DAT_O0 : std_logic_vector(31 downto 0);
 
   signal ACK_O : std_logic;
 
   signal ACK_O : std_logic;
 
   signal serial_out : std_logic;
 
   signal serial_out : std_logic;
 
 
 
 
 
   -- Clock period definitions (1.8432MHz)
 
   -- Clock period definitions (1.8432MHz)
 
   constant CLK_I_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
 
   constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
 
 
 
 
 
BEGIN
 
BEGIN
 
 
 
 
 
        -- Instantiate the Unit Under Test (UUT)
 
        -- Instantiate the Unit Under Test (UUT)
 
   uut: uart_wishbone_slave PORT MAP (
 
   uut: uart_wishbone_slave PORT MAP (
Line 76... Line 76... 
   -- Stimulus process
 
   -- Stimulus process
 
   stim_proc: process
 
   stim_proc: process
 
   begin
 
   begin
 
      -- Reset the slave
 
      -- Reset the slave
 
                RST_I <= '1';
 
                RST_I <= '1';
 
      wait for 1 ns;
 
      wait for CLK_I_period;
 
                RST_I <= '0';
 
                RST_I <= '0';
 
                wait for CLK_I_period*3;
 
                wait for CLK_I_period;
 
 
 
 
 
      -- Configure the clock... 
      -- Configure the clock... 
                ADR_I0 <= "00";
 
                ADR_I0 <= "00";
 
                WE_I <= '1';
 
                WE_I <= '1';
 
                STB_I <= '1';
 
                STB_I <= '1';
Line 113... Line 113... 
                WE_I <= '0';
 
                WE_I <= '0';
 
                STB_I <= '0';
 
                STB_I <= '0';
 
                ADR_I0 <= (others => 'U');
 
                ADR_I0 <= (others => 'U');
 
                wait for CLK_I_period;
 
                wait for CLK_I_period;
 
 
 
 
 
 
 
                -- Ask to send some data...(0xC4)
 
 
 
                ADR_I0 <= "11";
 
 
 
                WE_I <= '1';
 
 
 
                STB_I <= '1';
 
 
 
 
 
                -- Receive data...
 
                -- Receive data...
 
                -- Receive 0x55 value (01010101)
 
                -- Receive 0x55 value (01010101)
 
                serial_in <= '0'; -- Start bit
 
                serial_in <= '0'; -- Start bit
 
                wait for 8.68 us;
 
                wait for 8.68 us;
 
 
 
 
Line 139... Line 144... 
 
 
 
 
                -- Stop bit here
 
                -- Stop bit here
 
                serial_in <= '1';
 
                serial_in <= '1';
 
                wait for CLK_I_period*20;
 
                wait for CLK_I_period*20;
 
 
 
 
 
 
 
                wait until ACK_O = '1';
 
 
 
                WE_I <= '0';
 
 
 
                STB_I <= '0';
 
 
 
                wait for CLK_I_period;
 
 
 
 
 
      -- Stop Simulation
 
      -- Stop Simulation
 
                assert false report "NONE. End of simulation." severity failure;
 
                assert false report "NONE. End of simulation." severity failure;
 
   end process;
 
   end process;
 
 
 
 
 
END;
 
END;

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