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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 18 and 19
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| Rev 18 |
Rev 19 |
| Line 76... |
Line 76... |
-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- Reset the slave
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-- Reset the slave
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RST_I <= '1';
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RST_I <= '1';
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serial_in <= '1';
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wait for CLK_I_period;
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wait for CLK_I_period;
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RST_I <= '0';
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RST_I <= '0';
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wait for CLK_I_period;
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wait for CLK_I_period;
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-- Configure the clock...
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-- Configure the clock...
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| Line 111... |
Line 112... |
DAT_I0 <= x"000000C4";
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DAT_I0 <= x"000000C4";
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wait until ACK_O = '1';
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wait until ACK_O = '1';
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WE_I <= '0';
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WE_I <= '0';
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STB_I <= '0';
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STB_I <= '0';
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ADR_I0 <= (others => 'U');
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ADR_I0 <= (others => 'U');
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wait for CLK_I_period;
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wait for CLK_I_period*500;
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-- Ask to send some data...(0xC4)
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-- Receive data
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ADR_I0 <= "11";
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ADR_I0 <= "11";
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WE_I <= '1';
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WE_I <= '0';
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STB_I <= '1';
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STB_I <= '1';
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wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!)
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-- Receive data...
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-- Receive data...
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-- Receive 0x55 value (01010101)
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-- Receive 0x55 value (01010101)
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serial_in <= '0'; -- Start bit
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serial_in <= '0'; -- Start bit
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wait for 8.68 us;
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wait for 8.68 us;
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| Line 142... |
Line 144... |
serial_in <= '0';
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serial_in <= '0';
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wait for 8.68 us;
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wait for 8.68 us;
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait for CLK_I_period*20;
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wait until ACK_O = '1';
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wait until ACK_O = '1';
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WE_I <= '0';
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wait for CLK_I_period*100;
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STB_I <= '0';
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wait for CLK_I_period;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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