URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 19 and 20
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 19 |
Rev 20 |
| Line 114... |
Line 114... |
WE_I <= '0';
|
WE_I <= '0';
|
STB_I <= '0';
|
STB_I <= '0';
|
ADR_I0 <= (others => 'U');
|
ADR_I0 <= (others => 'U');
|
wait for CLK_I_period*500;
|
wait for CLK_I_period*500;
|
|
|
-- Receive data
|
-- Receive data from serial
|
ADR_I0 <= "11";
|
ADR_I0 <= "11";
|
WE_I <= '0';
|
WE_I <= '0';
|
STB_I <= '1';
|
STB_I <= '1';
|
wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!)
|
wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!)
|
|
|
-- Receive data...
|
-- Receive data... (Should work by retainning the last received value...)
|
-- Receive 0x55 value (01010101)
|
-- Receive 0x55 value (01010101)
|
serial_in <= '0'; -- Start bit
|
serial_in <= '0'; -- Start bit
|
wait for 8.68 us;
|
wait for 8.68 us;
|
|
|
serial_in <= '1';
|
serial_in <= '1';
|
| Line 147... |
Line 147... |
-- Stop bit here
|
-- Stop bit here
|
serial_in <= '1';
|
serial_in <= '1';
|
|
|
wait until ACK_O = '1';
|
wait until ACK_O = '1';
|
wait for CLK_I_period*100;
|
wait for CLK_I_period*100;
|
|
STB_I <= '0';
|
|
wait for CLK_I_period*100;
|
|
|
|
-- Read byte sent...
|
|
ADR_I0 <= "10";
|
|
WE_I <= '0';
|
|
STB_I <= '1';
|
|
wait until ACK_O = '1';
|
|
wait for CLK_I_period*100;
|
|
|
-- Stop Simulation
|
-- Stop Simulation
|
assert false report "NONE. End of simulation." severity failure;
|
assert false report "NONE. End of simulation." severity failure;
|
end process;
|
end process;
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.