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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 19 and 20
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| Rev 19 |
Rev 20 |
| Line 114... |
Line 114... |
WE_I <= '0';
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WE_I <= '0';
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STB_I <= '0';
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STB_I <= '0';
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ADR_I0 <= (others => 'U');
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ADR_I0 <= (others => 'U');
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wait for CLK_I_period*500;
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wait for CLK_I_period*500;
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-- Receive data
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-- Receive data from serial
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ADR_I0 <= "11";
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ADR_I0 <= "11";
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WE_I <= '0';
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WE_I <= '0';
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STB_I <= '1';
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STB_I <= '1';
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wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!)
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wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!)
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-- Receive data...
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-- Receive data... (Should work by retainning the last received value...)
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-- Receive 0x55 value (01010101)
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-- Receive 0x55 value (01010101)
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serial_in <= '0'; -- Start bit
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serial_in <= '0'; -- Start bit
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wait for 8.68 us;
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wait for 8.68 us;
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serial_in <= '1';
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serial_in <= '1';
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| Line 147... |
Line 147... |
-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait until ACK_O = '1';
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wait until ACK_O = '1';
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wait for CLK_I_period*100;
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wait for CLK_I_period*100;
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STB_I <= '0';
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wait for CLK_I_period*100;
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-- Read byte sent...
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ADR_I0 <= "10";
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WE_I <= '0';
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STB_I <= '1';
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wait until ACK_O = '1';
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wait for CLK_I_period*100;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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