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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 23 and 24
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| Rev 23 |
Rev 24 |
| Line 142... |
Line 142... |
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-- Stop bit here
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-- Stop bit here
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serial_in <= '1';
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serial_in <= '1';
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wait for CLK_I_period*5000;
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wait for CLK_I_period*5000;
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-- Check content by reading the register (Should be 0x55)
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ADR_I0 <= "11";
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WE_I <= '0';
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STB_I <= '1';
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wait until ACK_O = '1';
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STB_I <= '0';
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ADR_I0 <= (others => 'U');
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wait for CLK_I_period*5000;
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-- Ask to send some data...(0x55)
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ADR_I0 <= "10";
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WE_I <= '1';
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STB_I <= '1';
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DAT_I0 <= x"00000055";
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wait until ACK_O = '1';
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WE_I <= '0';
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STB_I <= '0';
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ADR_I0 <= (others => 'U');
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wait for CLK_I_period*5000;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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