URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 24 and 36

Rev 24	Rev 36
Line 49...	Line 49...
`-- Clock period definitions (1.8432MHz)`	`-- Clock period definitions (1.8432MHz)`
`constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)`	`constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`--! Instantiate the Unit Under Test (UUT)`
`uut: uart_wishbone_slave PORT MAP (`	`uut: uart_wishbone_slave PORT MAP (`
`RST_I => RST_I,`	`RST_I => RST_I,`
`CLK_I => CLK_I,`	`CLK_I => CLK_I,`
`ADR_I0 => ADR_I0,`	`ADR_I0 => ADR_I0,`
`DAT_I0 => DAT_I0,`	`DAT_I0 => DAT_I0,`