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ARCHITECTURE behavior OF testUart_wishbone_slave IS
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ARCHITECTURE behavior OF testUart_wishbone_slave IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT uart_wishbone_slave
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COMPONENT uart_wishbone_slave
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PORT(
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Port ( RST_I : in STD_LOGIC; --! Reset Input
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RST_I : IN std_logic;
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CLK_I : in STD_LOGIC; --! Clock Input
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CLK_I : IN std_logic;
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ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0); --! Address input
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ADR_I0 : IN std_logic_vector(1 downto 0);
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DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0); --! Data Input 0
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DAT_I0 : IN std_logic_vector(31 downto 0);
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DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0); --! Data Output 0
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DAT_O0 : OUT std_logic_vector(31 downto 0);
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WE_I : in STD_LOGIC; --! Write enable input
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WE_I : IN std_logic;
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STB_I : in STD_LOGIC; --! Strobe input (Works like a chip select)
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STB_I : IN std_logic;
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ACK_O : out STD_LOGIC; --! Ack output
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ACK_O : OUT std_logic;
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serial_in : IN std_logic;
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-- NON-WISHBONE Signals
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data_Avaible : out std_logic; -- Indicate that the receiver module got something
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serial_in : in std_logic; --! Uart serial input
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serial_out : OUT std_logic
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data_Avaible : out std_logic; --! Flag to indicate data avaible
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serial_out : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal RST_I : std_logic := '0';
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signal RST_I : std_logic := '0'; --! Signal to connect with UUT
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signal CLK_I : std_logic := '0';
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signal CLK_I : std_logic := '0'; --! Signal to connect with UUT
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signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0');
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signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0'); --! Signal to connect with UUT
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signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0');
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signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0'); --! Signal to connect with UUT
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signal WE_I : std_logic := '0';
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signal WE_I : std_logic := '0';
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signal STB_I : std_logic := '0';
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signal STB_I : std_logic := '0';
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signal serial_in : std_logic := '0';
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signal serial_in : std_logic := '0';
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--Outputs
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--Outputs
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signal DAT_O0 : std_logic_vector(31 downto 0);
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signal DAT_O0 : std_logic_vector(31 downto 0); --! Signal to connect with UUT
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signal ACK_O : std_logic;
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signal ACK_O : std_logic; --! Signal to connect with UUT
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signal serial_out : std_logic;
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signal serial_out : std_logic; --! Signal to connect with UUT
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signal data_Avaible : std_logic;
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signal data_Avaible : std_logic; --! Signal to connect with UUT
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-- Clock period definitions (1.8432MHz)
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-- Clock period definitions (1.8432MHz)
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constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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