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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [uart_communication_blocks.vhd] - Diff between revs 12 and 35
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| Rev 12 |
Rev 35 |
| Line 38... |
Line 38... |
end component;
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end component;
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component serial_receiver is
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component serial_receiver is
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Port (
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Port (
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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baudClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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end component;
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end component;
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| Line 68... |
Line 67... |
);
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);
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-- Instantiate serial_receiver
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-- Instantiate serial_receiver
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uReceiver : serial_receiver port map(
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uReceiver : serial_receiver port map(
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rst => rst,
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rst => rst,
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baudClk => baud_tick,
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baudOverSampleClk => baud_tick_oversample,
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baudOverSampleClk => baud_tick_oversample,
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serial_in => serial_in,
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serial_in => serial_in,
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data_ready => data_received_rx,
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data_ready => data_received_rx,
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data_byte => byte_rx
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data_byte => byte_rx
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);
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);
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