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--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
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--! @file
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--! @brief Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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serial_out : out std_logic; --! Uart serial out
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serial_out : out std_logic; --! Uart serial out
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serial_in : in std_logic; --! Uart serial in
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serial_in : in std_logic; --! Uart serial in
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start_tx : in STD_LOGIC); --! Initiate transmission
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start_tx : in STD_LOGIC); --! Initiate transmission
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end uart_communication_blocks;
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end uart_communication_blocks;
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--! @brief Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
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--! @details Declare used components for instantiation
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architecture Behavioral of uart_communication_blocks is
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architecture Behavioral of uart_communication_blocks is
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-- Declare components...
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-- Declare components...
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component baud_generator is
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component baud_generator is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Reset Input
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; --! Clock input
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); --! Number of cycles to wait for baud generation
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baud_oversample : out std_logic;
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baud_oversample : out std_logic; --! Oversample(8x) version of baud (Used on serial_receiver)
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baud : out STD_LOGIC);
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baud : out STD_LOGIC); --! Baud generation output (Used on serial_transmitter)
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end component;
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end component;
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component serial_transmitter is
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component serial_transmitter is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Reset input
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baudClk : in STD_LOGIC;
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baudClk : in STD_LOGIC; --! Baud rate clock input
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_sent : out STD_LOGIC;
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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serial_out : out STD_LOGIC);
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serial_out : out STD_LOGIC); --! Uart serial output
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end component;
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end component;
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component serial_receiver is
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component serial_receiver is
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Port (
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Port (
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rst : in STD_LOGIC;
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rst : in STD_LOGIC; --! Reset input
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baudOverSampleClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC; --! Baud oversampled 8x (Best way to detect start bit)
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serial_in : in STD_LOGIC;
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serial_in : in STD_LOGIC; --! Uart serial input
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data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC; --! Data received and ready to be read
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0)); --! Data byte received
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end component;
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end component;
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signal baud_tick : std_logic;
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signal baud_tick : std_logic;
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signal baud_tick_oversample : std_logic;
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signal baud_tick_oversample : std_logic;
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begin
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begin
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--! Instantiate baud generator
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--! Instantiate baud generator
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