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Line 4... |
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity uart_control is
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entity uart_control is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; -- Global reset
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clk : in STD_LOGIC;
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clk : in STD_LOGIC; -- Global clock
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WE : in STD_LOGIC;
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WE : in STD_LOGIC; -- Write enable
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reg_addr : in STD_LOGIC_VECTOR (1 downto 0);
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reg_addr : in STD_LOGIC_VECTOR (1 downto 0); -- Register address
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DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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start : in std_logic; -- Start (Strobe)
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DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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done : out std_logic; -- Done (ACK)
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tx_busy : in STD_LOGIC;
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DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
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rx_ready : in STD_LOGIC);
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DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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baud_wait : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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tx_data_sent : in STD_LOGIC; -- Signal comming from serial_transmitter
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rx_data_ready : in STD_LOGIC); -- Signal comming from serial_receiver
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end uart_control;
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end uart_control;
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_out : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_receive : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_in : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_transmitt : std_logic_vector((nBitsLarge-1) downto 0);
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signal controlStates : uartControl;
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signal controlStates : uartControl;
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signal sigDivRst : std_logic;
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signal sigDivRst : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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| Line 51... |
Line 56... |
numerator => sigDivNumerator,
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numerator => sigDivNumerator,
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divident => sigDivDividend,
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divident => sigDivDividend,
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done => sigDivDone
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done => sigDivDone
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);
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);
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-- Process that populate/read the uart control registers
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-- Process that read uart control registers
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process (rst, clk, reg_addr,WE)
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begin
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if rising_edge(clk) then
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if (WE = '0') and (start = '1') then
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case reg_addr is
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when "00" =>
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DAT_O <= config_clk;
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when "01" =>
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DAT_O <= config_baud;
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when "10" =>
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-- Byte that will be transmitted
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DAT_O <= "0000000000000000000000000" & byte_to_transmitt;
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when "11" =>
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-- Byte that will be received
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DAT_O <= "0000000000000000000000000" & byte_to_receive;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process;
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-- Process that populate the uart control registers
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process (rst, clk, reg_addr,WE)
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process (rst, clk, reg_addr,WE)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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config_clk <= (others => '0');
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config_clk <= (others => '0');
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config_baud <= (others => '0');
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config_baud <= (others => '0');
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byte_out <= (others => '0');
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byte_to_transmitt <= (others => '0');
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byte_in <= (others => '0');
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byte_to_receive <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if WE = '1' then
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if (WE = '1') and (start = '1') then
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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config_clk <= DAT_I;
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config_clk <= DAT_I;
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when "01" =>
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when "01" =>
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config_baud <= DAT_I;
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config_baud <= DAT_I;
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when "10" =>
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when "10" =>
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byte_out <= DAT_I((nBits-1) downto 0);
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-- Byte that will be transmitted
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byte_to_transmitt <= DAT_I((nBits-1) downto 0);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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| Line 79... |
Line 108... |
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-- Process to handle the next state logic
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-- Process to handle the next state logic
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process (rst, clk, reg_addr, WE)
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process (rst, clk, reg_addr, WE)
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variable baud_configured : std_logic;
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variable baud_configured : std_logic;
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variable clk_configured : std_logic;
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variable clk_configured : std_logic;
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variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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controlStates <= idle;
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controlStates <= idle;
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baud_configured <= '0';
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baud_configured <= '0';
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clk_configured <= '0';
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clk_configured <= '0';
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div_result_baud_wait <= (others => '0');
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done <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case controlStates is
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case controlStates is
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when idle =>
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when idle =>
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done <= '0';
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-- Go to config state
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-- Go to config state
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if (reg_addr = "00") and (WE = '1') then
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if (reg_addr = "00") and (WE = '1') then
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controlStates <= config_state_clk;
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controlStates <= config_state_clk;
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clk_configured <= '1';
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clk_configured <= '1';
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elsif (reg_addr = "01") and (WE = '1') then
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elsif (reg_addr = "01") and (WE = '1') then
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Line 135... |
sigDivRst <= '1';
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sigDivRst <= '1';
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sigDivNumerator <= config_clk;
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sigDivNumerator <= config_clk;
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if baud_configured = '0' then
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if baud_configured = '0' then
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-- Baud not configured yet so wait for it...
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-- Baud not configured yet so wait for it...
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controlStates <= idle;
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controlStates <= idle;
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done <= '1';
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else
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else
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-- If already configured wait for division completion...
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-- If already configured wait for division completion...
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controlStates <= start_division;
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controlStates <= start_division;
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end if;
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end if;
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Line 147... |
sigDivRst <= '1';
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sigDivRst <= '1';
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sigDivDividend <= config_baud;
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sigDivDividend <= config_baud;
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if clk_configured = '0' then
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if clk_configured = '0' then
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-- Clock not configured yet so wait for it...
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-- Clock not configured yet so wait for it...
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controlStates <= idle;
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controlStates <= idle;
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done <= '1';
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else
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else
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-- If already configured wait for division completion...
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-- If already configured wait for division completion...
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controlStates <= start_division;
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controlStates <= start_division;
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end if;
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end if;
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Line 161... |
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when wait_division =>
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when wait_division =>
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if sigDivDone = '0' then
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if sigDivDone = '0' then
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controlStates <= wait_division;
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controlStates <= wait_division;
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else
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else
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-- Division done, configure the Baud generator
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-- Division done, get the result to put on the wait_cycles signal of the baud generator
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div_result_baud_wait := sigDivQuotient;
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controlStates <= config_state_baud_generator;
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end if;
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when config_state_baud_generator =>
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-- Configure the wait_cycle for the desired baud rate...
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baud_wait <= div_result_baud_wait;
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controlStates <= rx_tx_state;
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done <= '1';
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-- Control the serial_receiver or serial_transmitter block
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when rx_tx_state =>
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controlStates <= rx_tx_state;
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if (WE = '1') and (start = '1') then
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if reg_addr = "10" then
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controlStates <= tx_state_wait;
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done <= '0';
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end if;
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end if;
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if (WE = '0') and (start = '1') then
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if reg_addr = "11" then
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controlStates <= rx_state_wait;
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done <= '0';
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end if;
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end if;
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-- Send data and wait to transmit
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when tx_state_wait =>
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data_byte_tx <= byte_to_transmitt;
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if tx_data_sent = '0' then
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controlStates <= tx_state_wait;
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else
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controlStates <= rx_tx_state;
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done <= '1';
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end if;
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end if;
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-- Receive data and wait to receive
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when rx_state_wait =>
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if rx_data_ready = '1' then
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byte_to_receive <= data_byte_rx;
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done <= '1';
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controlStates <= rx_tx_state;
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else
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controlStates <= rx_state_wait;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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