| Line 22... |
Line 22... |
end uart_control;
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end uart_control;
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_receive : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_receive : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmitt : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0);
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signal controlStates : uartControl;
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signal controlStates : uartControl;
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signal sigDivRst : std_logic;
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signal sigDivRst : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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| Line 68... |
Line 68... |
DAT_O <= config_clk;
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DAT_O <= config_clk;
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when "01" =>
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when "01" =>
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DAT_O <= config_baud;
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DAT_O <= config_baud;
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when "10" =>
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when "10" =>
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-- Byte that will be transmitted
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-- Byte that will be transmitted
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DAT_O <= "0000000000000000000000000" & byte_to_transmitt;
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DAT_O <= "000000000000000000000000" & byte_to_transmitt;
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when "11" =>
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when "11" =>
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-- Byte that will be received
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-- Byte that will be received
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DAT_O <= "0000000000000000000000000" & byte_to_receive;
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DAT_O <= "000000000000000000000000" & byte_to_receive;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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| Line 86... |
Line 86... |
begin
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begin
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if rst = '1' then
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if rst = '1' then
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config_clk <= (others => '0');
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config_clk <= (others => '0');
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config_baud <= (others => '0');
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config_baud <= (others => '0');
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byte_to_transmitt <= (others => '0');
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byte_to_transmitt <= (others => '0');
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byte_to_receive <= (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if (WE = '1') and (start = '1') then
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if (WE = '1') and (start = '1') then
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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config_clk <= DAT_I;
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config_clk <= DAT_I;
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| Line 112... |
Line 111... |
variable clk_configured : std_logic;
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variable clk_configured : std_logic;
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variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0);
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variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0);
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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controlStates <= idle;
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controlStates <= idle;
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baud_configured <= '0';
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baud_configured := '0';
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clk_configured <= '0';
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clk_configured := '0';
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div_result_baud_wait <= (others => '0');
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div_result_baud_wait := (others => '0');
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done <= '0';
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done <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case controlStates is
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case controlStates is
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when idle =>
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when idle =>
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done <= '0';
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done <= '0';
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-- Go to config state
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-- Go to config state
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if (reg_addr = "00") and (WE = '1') then
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if (reg_addr = "00") and (WE = '1') then
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controlStates <= config_state_clk;
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controlStates <= config_state_clk;
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clk_configured <= '1';
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clk_configured := '1';
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elsif (reg_addr = "01") and (WE = '1') then
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elsif (reg_addr = "01") and (WE = '1') then
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controlStates <= config_state_baud;
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controlStates <= config_state_baud;
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baud_configured <= '1';
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baud_configured := '1';
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end if;
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end if;
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when config_state_clk =>
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when config_state_clk =>
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sigDivRst <= '1';
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sigDivRst <= '1';
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sigDivNumerator <= config_clk;
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sigDivNumerator <= config_clk;
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