| Line 16... |
Line 16... |
DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
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tx_start : out std_logic; -- Signal to start sending serial data...
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rst_comm_blocks : out std_logic; -- Reset Communication blocks
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rx_data_ready : in std_logic); -- Signal comming from serial_receiver
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rx_data_ready : in std_logic); -- Signal comming from serial_receiver
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end uart_control;
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end uart_control;
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|
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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| Line 118... |
Line 119... |
clk_configured := '0';
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clk_configured := '0';
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div_result_baud_wait := (others => '0');
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div_result_baud_wait := (others => '0');
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done <= '0';
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done <= '0';
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sigDivRst <= '1';
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sigDivRst <= '1';
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rst_comm_blocks <= '1';
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rst_comm_blocks <= '1';
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tx_start <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case controlStates is
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case controlStates is
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when idle =>
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when idle =>
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done <= '0';
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done <= '0';
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-- Go to config state
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-- Go to config state
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| Line 177... |
Line 179... |
done <= '1';
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done <= '1';
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|
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-- Control the serial_receiver or serial_transmitter block
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-- Control the serial_receiver or serial_transmitter block
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when rx_tx_state =>
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when rx_tx_state =>
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rst_comm_blocks <= '0';
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rst_comm_blocks <= '0';
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tx_start <= '0';
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controlStates <= rx_tx_state;
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controlStates <= rx_tx_state;
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if (WE = '1') and (start = '1') then
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if (WE = '1') and (start = '1') then
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if reg_addr = "10" then
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if reg_addr = "10" then
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controlStates <= tx_state_wait;
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controlStates <= tx_state_wait;
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done <= '0';
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done <= '0';
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| Line 195... |
Line 198... |
end if;
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end if;
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|
|
|
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-- Send data and wait to transmit
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-- Send data and wait to transmit
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when tx_state_wait =>
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when tx_state_wait =>
|
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tx_start <= '1';
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data_byte_tx <= byte_to_transmitt;
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data_byte_tx <= byte_to_transmitt;
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if tx_data_sent = '0' then
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if tx_data_sent = '0' then
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controlStates <= tx_state_wait;
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controlStates <= tx_state_wait;
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else
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else
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controlStates <= rx_tx_state;
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controlStates <= rx_tx_state;
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