| Line 31... |
Line 31... |
signal controlStates : uartControl;
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signal controlStates : uartControl;
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signal sigDivRst : std_logic;
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signal sigDivRst : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0);
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--signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
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signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
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-- Divisor component
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-- Divisor component
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component divisor is
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component divisor is
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| Line 52... |
Line 52... |
-- Instantiate block for calculate division
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-- Instantiate block for calculate division
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uDiv : divisor port map (
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uDiv : divisor port map (
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rst => sigDivRst,
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rst => sigDivRst,
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clk => clk,
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clk => clk,
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quotient => sigDivQuotient,
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quotient => sigDivQuotient,
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reminder => sigDivReminder,
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reminder => open, -- Indicates that this port will not be connected to anything
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numerator => sigDivNumerator,
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numerator => sigDivNumerator,
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divident => sigDivDividend,
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divident => sigDivDividend,
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done => sigDivDone
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done => sigDivDone
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);
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);
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| Line 82... |
Line 82... |
end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Process that populate the uart control registers
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-- Process that populate the uart control registers
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process (rst, clk, reg_addr,WE)
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process (rst, clk, reg_addr,WE,start)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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config_clk <= (others => '0');
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config_clk <= (others => '0');
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config_baud <= (others => '0');
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config_baud <= (others => '0');
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byte_to_transmitt <= (others => '0');
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byte_to_transmitt <= (others => '0');
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