| Line 24... |
Line 24... |
end uart_control;
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end uart_control;
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|
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architecture Behavioral of uart_control is
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architecture Behavioral of uart_control is
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
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signal byte_to_receive : std_logic_vector((nBits-1) downto 0);
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--signal byte_to_receive : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0);
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signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0);
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signal controlStates : uartControl;
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signal controlStates : uartControl;
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|
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signal sigDivRst : std_logic;
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signal sigDivRst : std_logic;
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signal sigDivDone : std_logic;
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signal sigDivDone : std_logic;
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| Line 59... |
Line 59... |
divident => sigDivDividend,
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divident => sigDivDividend,
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done => sigDivDone
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done => sigDivDone
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);
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);
|
|
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-- Process that read uart control registers
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-- Process that read uart control registers
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process (rst, clk, reg_addr,WE)
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process (rst, reg_addr, WE, start, byte_to_transmitt, data_byte_rx, rx_data_ready, config_clk, config_baud)
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begin
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begin
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if rising_edge(clk) then
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if rst = '1' then
|
|
DAT_O <= (others => 'Z');
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else
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if (WE = '0') and (start = '1') then
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if (WE = '0') and (start = '1') then
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case reg_addr is
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case reg_addr is
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when "00" =>
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when "00" =>
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DAT_O <= config_clk;
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DAT_O <= config_clk;
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when "01" =>
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when "01" =>
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| Line 73... |
Line 75... |
when "10" =>
|
when "10" =>
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-- Byte that will be transmitted
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-- Byte that will be transmitted
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DAT_O <= "000000000000000000000000" & byte_to_transmitt;
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DAT_O <= "000000000000000000000000" & byte_to_transmitt;
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when "11" =>
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when "11" =>
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-- Byte that will be received
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-- Byte that will be received
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DAT_O <= "000000000000000000000000" & byte_to_receive;
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if rx_data_ready = '1' then
|
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DAT_O <= "000000000000000000000000" & data_byte_rx;
|
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--DAT_O <= "000000000000000000000000" & byte_to_receive;
|
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else
|
|
DAT_O <= (others => 'Z');
|
|
end if;
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when others =>
|
when others =>
|
null;
|
DAT_O <= (others => 'Z');
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end case;
|
end case;
|
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else
|
|
DAT_O <= (others => 'Z');
|
end if;
|
end if;
|
end if;
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end if;
|
end process;
|
end process;
|
|
|
-- Process that populate the uart control registers
|
-- Process that populate the uart control registers
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| Line 106... |
Line 115... |
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Process to handle the next state logic
|
-- Process to handle the next state logic
|
process (rst, clk, reg_addr, WE)
|
process (rst, clk, reg_addr, WE, start)
|
variable baud_configured : std_logic;
|
variable baud_configured : std_logic;
|
variable clk_configured : std_logic;
|
variable clk_configured : std_logic;
|
variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0);
|
variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0);
|
begin
|
begin
|
if rst = '1' then
|
if rst = '1' then
|
| Line 120... |
Line 129... |
div_result_baud_wait := (others => '0');
|
div_result_baud_wait := (others => '0');
|
done <= '0';
|
done <= '0';
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sigDivRst <= '1';
|
sigDivRst <= '1';
|
rst_comm_blocks <= '1';
|
rst_comm_blocks <= '1';
|
tx_start <= '0';
|
tx_start <= '0';
|
|
--byte_to_receive <= (others => 'Z');
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
case controlStates is
|
case controlStates is
|
when idle =>
|
when idle =>
|
done <= '0';
|
done <= '0';
|
-- Go to config state
|
-- Go to config state
|
| Line 191... |
Line 201... |
end if;
|
end if;
|
|
|
if (WE = '0') and (start = '1') then
|
if (WE = '0') and (start = '1') then
|
if reg_addr = "11" then
|
if reg_addr = "11" then
|
controlStates <= rx_state_wait;
|
controlStates <= rx_state_wait;
|
done <= '0';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
-- Send data and wait to transmit
|
-- Send data and wait to transmit
|
| Line 210... |
Line 219... |
end if;
|
end if;
|
|
|
-- Receive data and wait to receive
|
-- Receive data and wait to receive
|
when rx_state_wait =>
|
when rx_state_wait =>
|
if rx_data_ready = '1' then
|
if rx_data_ready = '1' then
|
byte_to_receive <= data_byte_rx;
|
-- Put an ack on the next cycle
|
done <= '1';
|
controlStates <= rx_state_ack;
|
controlStates <= rx_tx_state;
|
|
else
|
else
|
controlStates <= rx_state_wait;
|
controlStates <= rx_state_wait;
|
|
done <= '0';
|
end if;
|
end if;
|
|
|
|
-- Ack that we got a value
|
|
when rx_state_ack =>
|
|
done <= '1';
|
|
controlStates <= rx_tx_state;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
